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FAQ - bq77PL900 FET drive information
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FAQ - bq77PL900 FET drive information by 17523
What is the intended application of the internal FET drive circuit of the bq77PL900 and what additional information is available so I can interface to my FETs?
The FET driver was expected to drive through a nominal 5k external resistor to the gate of a modestly sized FET and a 1M ohm typical gate to source resistor. A small capacitance may be added between the switching FET gate and source and one or more zeners may be needed to limit voltages during transients. The topology is shown in the datasheet functional block diagram. The specifications available in the datasheet show the voltage levels expected with the 1M load and transition times with a 20nF load.
Always refer to the latest datasheet for up to date information on the device.
The pins BAT and PACK serve both as power pins and the source voltage sense pin for the associated discharge or charge FET. The outputs are DSG and CHG respectively.
There is an internal 1M ohm nominal resistor between the power pin and the associated FET drive output. This helps keep the FET off when the device is shutdown. There is also a parasitic diode from the FET drive output to the power pin. Current in this diode should be limited to 200mA peak and 50mA continuous.
When the device is on, the output drive is different between the FETOFF and FETON states as shown in the datasheet rise and fall time characteristics. When the output is in the FETON state the output current flows through an internal 1k ohm resistor. The output current must be limited to protect the output from damage. Current should be limited to 11.4 mA peak, 6 mA RMS, 2.2 mA DC. When the output is in the FETOFF state it is clamped to the power pin and the output current does not go through the 1k internal resistor.
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