UCD 9240

Gerhard,

It may be possible to use the UCD9240--but it won't be easy.  The device and the Fusion design tool are set up to support a synchronous buck topology with input voltage between 5V and 16V and an output voltage between 0 and 16V.  So, here are the problems you would face: 

1)       The design tool will not simulate a SEPIC power stage so the compensation would have to be worked out by hand.  You might be able to get close by choosing Ls and Cs that make the plant transfer function in the design tool match the SEPIC power stage transfer function, then make a manual allowance for the D/(1-D)*Vin transfer function of a SEPIC stage.

2)       You will have to lie to the device an tell it that the current sense output is the output voltage.  The device input has an effective dynamic range of 0 to 1.6V. So set up your current sense circuit to generate, say, 1.00V at the rated current.  You could then build divider networks to set the 500V output voltage to be between 0 and 2.0V and feed this into the CS pin to have the device provide overvoltage protection.  Of course this will all be confusing and backward when queried on the PMBus.

The compensation will be the biggest challenge.  I would start with a low DC gain, set Fp2 to be 25% of the switching frequency and set the zeros to be at 1/2 and 2X the corner frequency of the power stage.  Then close the loop and look at the response to load steps or Vin steps in the regulated current.  To tune the transient performance, use the PID gain controls, increase the integral gain (this is also the DC gain) to improve the settle time until the overshoot becomes excessive, then increase the proportional and derivative gain to decrease the overshoot, then go back to increasing the integral gain.  working back and forth like this, you should be able to tune up the loop bandwidth. 

Good luck.

Mark Hagen

System's Engineer, Digital Power POL products