unable to get UCD3138 external sync working

hakan aydin

Other Parts Discussed in Thread: UCD3138

Hello,

We are running an open loop example DPWM code. Here's our setup: We have three DPWM modules active: 0, 1 and 2. All three have CLA_EN=0. Modules 0 and 1 output a PWM signal from both A and B channels, interleaved, each having a period of about P/8. So the waveforms look like:

|----_____________________|----_____________________|

|___----__________________|___----__________________|

|______----_______________|______----_______________|

|_________----____________|_________----____________|

Module 2 is setup such that it outputs another signal, which we intend to use as SYNC, in order to test external sync functionality:

|____________________-____|____________________-___|

Modules 0 and 1 have EXT_SYNC_EN = 1, Module 2 has that bit turned off.

With this configuration, when we connect the DPWM2 output to the SYNC_IN pin, we expect that the period of the DPWM0 and DPWM1 signals to be shorter, since we apply a sync pulse before the counter reaches the programmed period end. However, we see no difference with or without the SYNC signal.

Any ideas what we might be doing wrong?

By the way, what is the actual SYNC mechanism? Does the IC look at the rising edge of SYNC, falling edge of SYNC, or something else entirely? In the "data manual", SYNC pulse is defined to have a typical 256ns width, but does that apply to the case when SYNC is an output? What about when it is an input? Is there a requirement?

over 10 years ago

0 Sanatan Rajagopalan over 10 years ago

TI__Intellectual 1270 points

Hi hakan aydin,

Did you connect DPWM 2 out put to pin No 26 of the IC ? The IC uses the rising edge of the SYNC pin to reset the DPWM counter.

Here is a sample configuration to get the SYNC working:

#define SWITCHING_FREQUENCY (20)
#define HALF_PERIOD ((int)((1000000/SWITCHING_FREQUENCY)/8)) //half period in 4 nanosecond steps.
#define PERIOD (HALF_PERIOD * 2)  //define half period first, so period is guaranteed to be double half period.
#define PERIOD_HIGH_RES (PERIOD * 16)


void init_dpwm_0(void)
{
	Dpwm0Regs.DPWMCTRL0.bit.PWM_EN = 0;
	Dpwm0Regs.DPWMPRD.all = PERIOD_HIGH_RES;

	Dpwm0Regs.DPWMEV1.all =0;
	Dpwm0Regs.DPWMEV2.all =PERIOD_HIGH_RES/8; 


	Dpwm0Regs.DPWMEV3.all =	Dpwm0Regs.DPWMEV2.all-(PERIOD_HIGH_RES/32);
	Dpwm0Regs.DPWMEV4.all =Dpwm0Regs.DPWMEV3.all +(PERIOD_HIGH_RES/8) ; 
	
	Dpwm0Regs.DPWMCTRL0.bit.CLA_EN = 0; 
	Dpwm0Regs.DPWMCTRL2.bit.SAMPLE_TRIG_1_EN = 1; 
	Dpwm0Regs.DPWMCTRL1.bit.EXT_SYNC_EN=1;
	Dpwm0Regs.DPWMCTRL1.bit.EVENT_UP_SEL = 0; 


	Dpwm0Regs.DPWMCTRL0.bit.PWM_MODE = 0;

	Dpwm0Regs.DPWMINT.bit.PRD_INT_EN = 1;
	Dpwm0Regs.DPWMINT.bit.PRD_INT_SCALE = 0;



	Dpwm0Regs.DPWMCTRL0.bit.PWM_EN = 1;
}

void init_dpwm_1(void)
{
	Dpwm1Regs.DPWMCTRL0.bit.PWM_EN = 0;
	Dpwm1Regs.DPWMPRD.all = PERIOD_HIGH_RES;

	Dpwm1Regs.DPWMEV1.all =Dpwm0Regs.DPWMEV4.all-(PERIOD_HIGH_RES/32);
	Dpwm1Regs.DPWMEV2.all =Dpwm1Regs.DPWMEV1.all+PERIOD_HIGH_RES/8; 


	Dpwm1Regs.DPWMEV3.all =Dpwm1Regs.DPWMEV2.all-(PERIOD_HIGH_RES/32);
	Dpwm1Regs.DPWMEV4.all =Dpwm1Regs.DPWMEV3.all +(PERIOD_HIGH_RES/8) ; 
	
	Dpwm1Regs.DPWMCTRL0.bit.CLA_EN = 0;  
	Dpwm1Regs.DPWMCTRL2.bit.SAMPLE_TRIG_1_EN = 1;
	Dpwm1Regs.DPWMCTRL1.bit.EXT_SYNC_EN=1;
	Dpwm1Regs.DPWMCTRL1.bit.EVENT_UP_SEL = 0; 

	Dpwm1Regs.DPWMCTRL0.bit.PWM_MODE = 0;

	Dpwm1Regs.DPWMINT.bit.PRD_INT_EN = 1;
	Dpwm1Regs.DPWMINT.bit.PRD_INT_SCALE = 0;



	Dpwm1Regs.DPWMCTRL0.bit.PWM_EN = 1;
}
void init_dpwm_2(void)
{	Dpwm2Regs.DPWMCTRL0.bit.PWM_EN = 0;
	Dpwm2Regs.DPWMPRD.all = PERIOD_HIGH_RES;

	Dpwm2Regs.DPWMEV1.all =PERIOD_HIGH_RES *3/4;
	Dpwm2Regs.DPWMEV2.all =Dpwm2Regs.DPWMEV1.all+PERIOD_HIGH_RES/32; 


	Dpwm2Regs.DPWMEV3.all =Dpwm1Regs.DPWMEV2.all-(PERIOD_HIGH_RES/32);
	Dpwm2Regs.DPWMEV4.all =Dpwm1Regs.DPWMEV3.all +(PERIOD_HIGH_RES/8) ; 
	
	Dpwm2Regs.DPWMCTRL0.bit.CLA_EN = 0;  
	Dpwm2Regs.DPWMCTRL2.bit.SAMPLE_TRIG_1_EN = 1; 

	Dpwm2Regs.DPWMCTRL1.bit.EVENT_UP_SEL = 0; 

	Dpwm2Regs.DPWMCTRL0.bit.PWM_MODE = 0;

	Dpwm2Regs.DPWMINT.bit.PRD_INT_EN = 1;
	Dpwm2Regs.DPWMINT.bit.PRD_INT_SCALE = 0;



	Dpwm2Regs.DPWMCTRL0.bit.PWM_EN = 1;
}


void main()
{
         init_dpwm_0();
	init_dpwm_1();
	init_dpwm_2();

 for(;;);

0 michael over 9 years ago in reply to Sanatan Rajagopalan

Prodigy 170 points

hi,
ucd3138 of QFN40 package is used, does it have the sync function? if yes, how should I configure to use it as sync input?
thanks.

0 Ian Bower over 9 years ago in reply to michael

TI__Genius 17090 points

On the 40 pin QFN, sync is available on pin 8 and pin 21. Use the IOMUX register to configure one of those pins as a SYNC input.

0 michael over 9 years ago in reply to Ian Bower

Prodigy 170 points

I configure IOMUX register, but the SYNC(pin 8) doesn't work. I give a 150KHZ signal to pin 8, and configure dpwm0 synchronized to it, but there is no dpwm output at all. My codes are as follows：

MiscAnalogRegs.GLBIOEN.bit.ADC_EXT_TRIG_IO_EN = 0;//SPECIAL FUNCTION
MiscAnalogRegs.IOMUX.bit.EXT_TRIG_MUX_SEL = 2;//SYNC
LoopMuxRegs.SYNCCTRL.bit.SYNC_DIR = 1; //input

Dpwm0Regs.DPWMCTRL0.bit.PWM_EN = 0;

Dpwm0Regs.DPWMCTRL1.bit.GLOBAL_PERIOD_EN = 1;

Dpwm0Regs.DPWMEV1.all = 0;

Dpwm0Regs.DPWMEV2.all = 1000;

Dpwm0Regs.DPWMEV3.all = 10000;

Dpwm0Regs.DPWMEV4.all = Dpwm0Regs.DPWMEV3.all + Dpwm0Regs.DPWMEV2.all;

Dpwm0Regs.DPWMCTRL0.bit.CLA_EN = 0;

Dpwm0Regs.DPWMCTRL2.bit.SAMPLE_TRIG_1_EN = 0;

Dpwm0Regs.DPWMCTRL1.bit.EVENT_UP_SEL = 1;

Dpwm0Regs.DPWMCTRL0.bit.PWM_MODE = 0;

Dpwm0Regs.DPWMINT.bit.PRD_INT_EN = 0;

Dpwm0Regs.DPWMINT.bit.PRD_INT_SCALE = 0;

Dpwm0Regs.DPWMCTRL0.bit.PWM_EN = 1;

Dpwm0Regs.DPWMCTRL1.bit.EXT_SYNC_EN= 1;

0 michael over 9 years ago in reply to michael

Prodigy 170 points

On the 40 pin QFN, SYNC and TCK must be reconfigured as another function.

MiscAnalogRegs.GLBIOEN.bit.ADC_EXT_TRIG_IO_EN = 0;//SPECIAL FUNCTION

MiscAnalogRegs.IOMUX.bit.SYNC_MUX_SEL = 2;//

MiscAnalogRegs.IOMUX.bit.JTAG_CLK_MUX_SEL = 0;//default is 2

MiscAnalogRegs.IOMUX.bit.EXT_TRIG_MUX_SEL = 2;//SYNC

LoopMuxRegs.SYNCCTRL.bit.SYNC_DIR = 1; //input

So, it works well!

0 user4461939 over 8 years ago in reply to michael

Prodigy 85 points

I give a 200KHZ signal to pin 8(SYNC), and configure dpwm0 synchronized to it, but there is no dpwm output at all. My Demo is UCD3138HPFBVEM_029 , the chip is of the 40 pin QFN, what's the problem?
My codes are as follows：

#define SWITCHING_FREQUENCY (200)
#define HALF_PERIOD ((int)((1000000/SWITCHING_FREQUENCY)/8)) //half period in 4 nanosecond steps.
#define PERIOD (HALF_PERIOD * 2) //define half period first, so period is guaranteed to be double half period.
#define PERIOD_HIGH_RES (PERIOD * 16)

void init_dpwm_0(void)
{
MiscAnalogRegs.GLBIOEN.bit.ADC_EXT_TRIG_IO_EN = 0;//SPECIAL FUNCTION
MiscAnalogRegs.IOMUX.bit.SYNC_MUX_SEL = 2; //
MiscAnalogRegs.IOMUX.bit.JTAG_CLK_MUX_SEL = 0; //default is 2
MiscAnalogRegs.IOMUX.bit.EXT_TRIG_MUX_SEL = 2; //SYNC
LoopMuxRegs.SYNCCTRL.bit.SYNC_DIR = 1;

Dpwm0Regs.DPWMCTRL0.bit.PWM_EN = 0;
Dpwm0Regs.DPWMPRD.all = PERIOD_HIGH_RES;

Dpwm0Regs.DPWMEV1.all = 0;
Dpwm0Regs.DPWMEV2.all = PERIOD_HIGH_RES/8;

Dpwm0Regs.DPWMEV3.all = Dpwm0Regs.DPWMEV2.all-(PERIOD_HIGH_RES/32);
Dpwm0Regs.DPWMEV4.all = Dpwm0Regs.DPWMEV3.all +(PERIOD_HIGH_RES/8) ;

Dpwm0Regs.DPWMCTRL0.bit.CLA_EN = 0;
Dpwm0Regs.DPWMCTRL2.bit.SAMPLE_TRIG_1_EN = 1;
Dpwm0Regs.DPWMCTRL1.bit.EXT_SYNC_EN=1;
Dpwm0Regs.DPWMCTRL1.bit.EVENT_UP_SEL = 0;

Dpwm0Regs.DPWMCTRL0.bit.PWM_MODE = 0;

Dpwm0Regs.DPWMINT.bit.PRD_INT_EN = 1;
Dpwm0Regs.DPWMINT.bit.PRD_INT_SCALE = 0;

Dpwm0Regs.DPWMCTRL0.bit.PWM_EN = 1;

}
void init_gpio(void)
{
MiscAnalogRegs.IOMUX.bit.JTAG_DATA_MUX_SEL = 1; // Accommodate TDO/TDI pins for RXD/TXD use
MiscAnalogRegs.IOMUX.bit.UART_MUX_SEL = 0;
MiscAnalogRegs.GLBIOVAL.bit.FAULT2_IO_VALUE = 0; //debug state

// Set outputs to 0.
MiscAnalogRegs.GLBIOVAL.all = 0;
// 1 - Output, 0 - Input
MiscAnalogRegs.GLBIOOE.all = MASK_PGOOD | MASK_FAILURE | MASK_VINOK |
DPWM0A_GLBIO_BIT_MASK | DPWM0B_GLBIO_BIT_MASK |
DPWM1A_GLBIO_BIT_MASK | DPWM1B_GLBIO_BIT_MASK |
DPWM2A_GLBIO_BIT_MASK | DPWM2B_GLBIO_BIT_MASK |
DPWM3A_GLBIO_BIT_MASK | DPWM3B_GLBIO_BIT_MASK ;// MASK_VINOK |

MiscAnalogRegs.GLBIOEN.all = MASK_PGOOD | MASK_FAILURE | MASK_VINOK |
CONTROL_GLBIO_BIT_MASK;//0 = Input
}
void gpio_dpwm_on(void)
{
MiscAnalogRegs.GLBIOEN.all &= ~((Uint32)(DPWM0A_GLBIO_BIT_MASK | DPWM0B_GLBIO_BIT_MASK|
DPWM1A_GLBIO_BIT_MASK | DPWM1B_GLBIO_BIT_MASK|
DPWM2A_GLBIO_BIT_MASK | DPWM2B_GLBIO_BIT_MASK|
DPWM3A_GLBIO_BIT_MASK | DPWM3B_GLBIO_BIT_MASK));
}

void main()
{

volatile unsigned int dummy;
if(GioRegs.FAULTIN.bit.FLT2_IN == 1)// Re-Check pin assignment (ADC_EXT/SYNC may be?)
{
clear_integrity_word();
}
init_gpio();
gpio_dpwm_on();
init_dpwm_0();
for(;;)
{
if (erase_segment_counter > 0)
{
erase_task(); // Handle the DFlash segment erases
}
pmbus_handler();
}
}