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Doubt: Does UCD3138064 really support more than one independent peak current mode control simultaneously?

Other Parts Discussed in Thread: UCD3138064, UCD3138

Hi All

Currently, I try to develop interleaved boost converter with peak current mode control using UCD3138064. In its datasheet, it said the chip supports 3 independent peak current mode control. However, how do I set the register “PCM_FE_SEL” in Page 80 if I use Front End 1 and 2 for peak current mode control simultaneously?

Does this chip really support up more than one independent peak current mode control?


Best Regards

Tom

  • Hi,

    Anyone could help and use 2 peak current mode control simultaneously?

    Tom

  • Hi,

    Anyone have any idea and could help for using 2 peak current mode control simultaneously -  setting the register bit “PCM_FE_SEL” in ADPCMCTRL at P.80  of the manual "UCD3138 Digital Power Peripherals Programmer’s Manual"? I would be grateful if any experienced expert could have the answer.

    Thank you.

    Tom

  • Hi,

    Anyone have any idea and could help for using 2 peak current mode control simultaneously -  setting the register bit “PCM_FE_SEL” in ADPCMCTRL at P.80  of the manual "UCD3138 Digital Power Peripherals Programmer’s Manual"? I would be grateful if any experienced expert could have the answer.

    Thank you.

    Tom

  • Tom,

    Can you please clarify what it is you are trying to accomplish? As far as two independent PCM, this is not possible. You would need 4 Analog Front Ends and the UCD only provides 3. Are you trying to control 2 independent outputs?

    Have you looked at the PFC EVM code and settings for interleaved control in the PWR026 EVM of which we have provided the code already?

    There is also a good Appnote about designing an interleaved PFC for the UCD device: http://www.ti.com/lit/an/slua712/slua712.pdf

    Can you please send me some more information as to what it is you are trying to do? Thanks!

    -Regards,

    Brandon Vonk

  • Hi Brandon

                  

    I think you mentioned 4 AFEs is needed only in the case that 2 AFEs are used to generate 2 independent current references for 2 totally independent PCM control(other 2 AFEs for PCM comparators) but not for the interleaved converter as, in the converter, 2 PCM should share the same current reference. Therefore, 3 AFEs should be enough, am I right? ( 1 AFE for generating current reference and 2 AFEs for PCM comparators).

     

    However, we think 2 AFEs is enough for our project, interleaved boost DC-DC converter, if we input the current reference externally through one of the ADCs channels and set it into the ramp start value for slope compensation. Then, the 2 AFEs will only act as peak current mode comparators. For the sake of simplicity, we use our existing analog current reference as the current reference for the 2 PCM channels in UCD3138064 via a ADC channel so in principle it will save 1 AFE from generating current reference. Therefore, 2 AFEs should be enough, isn’t it?

     

    The question now is, how to set the register bit “PCM_FE_SEL” in the register ADPCMCTRL (P.80 in UCD3138 Digital Power Peripherals Programmer’s Manual) if using front-end 1 and 2 to implement 2 peak current mode control with half cycle delay without restricting the duty cycle below 50% in the interleaved topology. In UCD3138, we only could set it at a time. Will the UCD3138064 have the new register regarding to this issue so that we could implement the 2 PCM in the interleaved boost DC-DC converter?

     

    Yes, I have read the application notes and the code of PWR026 EVM about interleaved PFC. However, our project is interleaved boost DC-DC converter and we need the slope compensation to eliminate the sub-harmonic in peak current mode control which is not needed in the average current mode control.

     

    It would be great if you could give me some hints and clue. I am looking forward to hearing from you soon. Many thanks.

     

    Best Regards

     

    Tom