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UCD3138A: ADC buffer_en and sample and hold functionality

ziopaper
Intellectual 940 points
Part Number: UCD3138A

Hello,

I am having issues with one ADC reading affecting other channels. My configuration is as following:

- AD02 is configured for dual SH (BYPASS_EN = 3)

- AD04 (SEQ2) is configured for dual sampling (SEQ2_SH = 1)

- AD00 is sampled normally

- sampling freq is 267KS/s

- the impedance on AD00 is 13.5kohm in parallel to 0.1uF (it is a 3Mohm divider with 13.5kohm on the bottom side, between AD00 pin and GND)

- impedance at AD02 and AD04 is about 4kohm with 1nF in parallel

When the voltage at AD02 is changed from 0 to 2.5V, the value corresponding to AD00 changes of about 35. The voltage at AD00 changes of about 10mV (for a value of 35 I would have expected 20mV but this is not the issue). The problem here that with a 3Mohm divider, 10mV difference measured mean 2.2V error at the top of the divider, not terrible but I am looking to improve this.

I cannot lower the impedance at AD00 pin. 

Can I use ADC_SH_BUFFER_EN? While AD02 is being used for dual sampling?

If I set BYPASS_EN = 2 (010), this should mean that the SH buffer is active for both AD00 and AD02. Is this correct?

Now, with Bypass_en = 2, SEQ2_SH = 1, and BUFFER_EN = 1, is it operation correct? The migration guide, in the section about BUFFER_EN mentions to "Make sure that there are no SEQx_SH bits set", so I am wandering if this configuration is acceptable of if there could be any issues with it. 

Thank you

  • 0
    TI__Genius 17090 points

    Marco, I'm pretty sure you can't do it.  You can either use the sample and hold, which requires the buffer, or you can use the buffer by itself.  You can't use it twice. 

  • 0 in reply to Ian Bower
    TI__Genius 17090 points
    After thinking about it more, what I would do is to read that particular signal less often. I'm guessing that its the Vout from a PFC, which doesn't change very fast. If you are using single sweep mode on the ADC, you can normally read only Line and Neutral, and then once in a while, read Vout - probably a 1 KHz rate would be good enough. Reducing the effective sampling rate increases the input impedance on the ADC.

    To do this, the simplest way is to put the Vout at the end of the list of samples, and normally have the number of samples low so it doesn't get sampled. When you want to sample it, poll the ADC, and then increase the number of samples by 1 before starting the next set of conversions. After the next poll, reduce it again.

    You might need to put a bigger cap on there to take advantage of this.
  • 0 in reply to Ian Bower
    Intellectual 940 points
    Thank you Ian,

    reducing the sampling freq of AD03 improves the reading greatly. To obtain this, I rearranged the sequence to have AD03 sampled last as you suggested. When I do this, the error is now "transferred" to the first channel sampled after AD02 (to which voltage is applied).
    Before I had:
    AD03 error here
    AD00
    AD04
    AD02 voltage applied here

    now I have:
    AD00 error here
    AD04
    AD02 voltage applied here
    AD03 (sampled at much lower rate, so NOT sampled most of the time)

    The ADC is configured in single sweep, so I am wandering, am I simply seen the effect of the MUX cap charged to the value of AD02 voltage and not having enough time to discharge completely before sampling the next channel?

    Increasing the capacitance at AD00 reduced the error, as suggested in the technical reference

    thank you
  • 0 in reply to ziopaper
    TI__Genius 17090 points

    It's not the MUX cap you are seeing, it's the input cap of the ADC you are seeing.  Essentially the cap will still be charged to a value close to the value of the last signal sampled.  So the input impedance is really a function of the sampling rate, the capacitance and the level of the previous line sampled.