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UCD3138A: cycle by cycle current limit

Part Number: UCD3138A

Hello everybody,

in my application the DPWM signal should by interrupted by a current limit. Therefore I have used ACOMP-F and the pin has a positive offset voltage, so I will be able to detect, when the current will become negative polarity. Will the input voltage go below ZCD_THRESHOLD, the current DPWM cycle should be interrupted.

// enable ACOMP-F pin and connect to current limit on DPWM-1 (ZCD - zero current detection)
FaultMuxRegs.DPWM1CLIM.bit.ACOMP_F_EN      = 1;
FaultMuxRegs.ACOMPCTRL2.bit.ACOMP_F_SEL    = 0;
FaultMuxRegs.ACOMPCTRL2.bit.ACOMP_F_POL    = 0;
FaultMuxRegs.ACOMPCTRL2.bit.ACOMP_F_THRESH = ZCD_THRESHOLD;

In the DPWM module I have the following configurations:

// activate cycle by cycle current limit
Dpwm1Regs.DPWMCTRL0.bit.CBC_PWM_AB_EN    = 1;
Dpwm1Regs.DPWMCTRL0.bit.CBC_ADV_CNT_EN   = 1;
Dpwm1Regs.DPWMFLTCTRL.bit.CBC_MAX_COUNT  = 0;
Dpwm1Regs.DPWMFLTCTRL.bit.CBC_FAULT_EN   = 1;

Actually the ZCD does it's job as expected - but just a single time! Instead of re-activate DPWM at the next DPWM period, it keeps inactive! Just by disabling and enabling DPWM again, the DPWM module beginns to work - ...for a single time and the game beginns again!

In the technical reference manual, this behavior is described for a FAULT_AB detection, but not for the CLIM/CBC!

Has anyone an idea how to fix that?

Thanks for your assistance!

Kind regards,

Andy

  • Hi Andy,

    CBC current limit is different than CBC fault.
    CBC Fault means after a few or several CBC current limit events, latch off and looks like the FAULT_AB with a delay(CBC_MAX_COUNT).
    Just remove the Dpwm1Regs.DPWMFLTCTRL.bit.CBC_FAULT_EN = 1 and you should see the CBC current limit function as you expect.

    Regards,
  • Hi Yitzhak,

    thank you very much for your quick response. I tested Dpwm1Regs.DPWMFLTCTRL.bit.CBC_FAULT_EN = 0, but unfortunatelly the CBC current limit does not work as expected!

    DPWM1-A will charge the inductor, DPWM1-B will work as "ideal diode". By setting Dpwm1Regs.DPWMFLTCTRL.bit.CBC_FAULT_EN = 0, DPWM1-B will be HIGH for the rest of the DPWM cycle and will not be interrupted. This causes high currents, while the input ac voltage is low and the capacitor is loaded to (actually!) 140 V.

    Dpwm1Regs.DPWMFLTCTRL.bit.CBC_FAULT_EN = 1 (DPWM1-A will be interrupted):

    Dpwm1Regs.DPWMFLTCTRL.bit.CBC_FAULT_EN = 0 (DPWM1-A will not be interrupted):

    What am I doing wrong?

    Kind regards,

    Andy

  • Which DPWM mode are you in?

    Normal-mode (A -> D, B->(1-D))

    or

    Multi-mode     (A -> D, B->D)

    If you are in Normal mode , CBC only truncates A, and B actualy gets wider to follow the (1-D) relation. Therefore you can not expect CBC to truncate B.

    In Multi-mode CBC will potentialy truncate both A or B, depending on when it occurs compared to A or B pulses.

  • Currently I'm in normal mode, by setting "crossover" in the INTRA_MUX depending to the polarity of the input voltage.

    Following there is a drawing of my circuit:

    Is there another way to interrupt both DPWM1 channels at zero current detection, just for a single DPWM1 period? What's about the "Ideal Diode Emulation"?

    Isn't normal mode the best DPWM mode in this application? Which mode should be used instead?

    EDIT:

    I have made some tests with multi mode today. How do I ensure, that DPWM-A and DPWM-B will not be high at the same time? Sometimes I have seen both channels high! How to configure CBC for disable DPWM output at ZCD for just the rest of a DPWM period?

    Kind regards,

    Andy

  • Hi Andy,

    Multi-mode is not the answer to your requirements.
    If you have spare DPWMs, I think we could try to acheive what you need by the following configuration:

    1) We can set the other DPWM (Let's say DPWM1) to open loop normal mode with a close to 100% duty cycle, so the DPWM1A output is very wide.

    2) Connect the CBC signal so the falling edge of DPWM1A is truncated by the CBC.

    3) Now, we could use Edge_Gen to build a new waveform . The rising edge is the rising edge of DPWM0B and the falling edge is the falling edge of DPWM1A.

    4) With intramux we could have this waveform to come out of DPWM0B pin.

    I have not tested this, but looks like it worths a try. Please read about Edge-Gen in the manual.

    Regards,

  • Hi Yitzhak,

    thank you very much for your response and your assistance. Our design is a Totem Pole PFC, based on the TI Literature Numbers SLUP327 and SLUP328 (with some modifications). (Today I have seen, that you are one of the authors!) So, if the ZCD in the current design will not work, I am wondering how you did have fixed that.

    Is the ZCD possibly not needed in that application? In my opinion one of the FET works as charge pump for the inductor and the next step the other FET will pipe the energy nearly without loss. But when the inductors voltage goes below the capacitors voltage, a negative current will be able to damage this FET. So to switch off this FET after ZCD should be needed.

    Did you have found another way in your TTP-PFC to realize that?

    Just to have questioned: Would it be possible to get some source snippets of your application, just to see, how you have fixed that? I have written the complete firmware by myself, but now I'm stumble by that (simple?) issue. Some code snippets could be helpfull to find the solution...!

    Thanks in advance,

    Andy

  • Is this a single phase or interleaved application?
    Our current project does not apply ZCD and is a CCM mode solution.
  • It's like your project a CCM Totem-Pole Bridgeless PFC with a single phase input. It should be the base for a 24Vdc power supply.
    If your application doesn't apply ZCD: How did you prevent negative currents in the discharging part of the DPWM period?
  • We do not prevent negative current. The FETs in our EVM do not seem to be affected.
  • Okay, this will bring up some new questions...! In one of my last tests I have seen high negative currents in phases, when the duty of channel A (normal mode) is very low and channel B has a high 1-D. This is especially, when the input voltage is near zero crossing and the capacitor is loaded to (actually!) 140V. Actually I handle this with the CBC Fault, but this is just to safe my hardware.

    SLUP327:

    Is there a way to use the IDE to fix my problem?

    Tomorrow I will ask some of my colleagues, how I can go forward with this issue. After that I will reply again.

    Thank you very much for your assistance!

    Kind regards,

    Andy

  • I am just reffering to the released code that is 100% tested.
    Other ideas were intertained and could be persued by you.
    You can still implement ZCD, via what I have previously suggested:
    ----------------------------------------------------------------------
    If you have spare DPWMs, I think we could try to acheive what you need by the following configuration:

    1) We can set the other DPWM (Let's say DPWM1) to open loop normal mode with a close to 100% duty cycle, so the DPWM1A output is very wide.

    2) Connect the CBC signal so the falling edge of DPWM1A is truncated by the CBC.

    3) Now, we could use Edge_Gen to build a new waveform . The rising edge is the rising edge of DPWM0B and the falling edge is the falling edge of DPWM1A.

    4) With intramux we could have this waveform to come out of DPWM0B pin.
    ---------------------------------------------------------------------------------
    Or alternatively you could use the Sync pin to not only terminate the Sync-FET pulse, but also shorten the whole period and immediately start a new period. (Transition mode control).

    Regards,
  • Hello Yitzhak,

    yesterday I found an alternative way to prevent negative currents in the second phase of the DPWM. So I have an interim solution for now. These "alternative way" may not be the final solution, but I can go forward to get the PFC running. Maybe later I will try other ways (like your suggestion!), when the project phase is in a more steady state - or at least when I am situated in a "dead-end street...!

    Thank you very much for your assistance!

    Kind regards,

    Andy

  • Glad the issue is resolved. Please let me know if I can help with anything.

    Regards,