UCD3138: DPWM Module

Hello, We are using UCD3138 for an active clamp forward converter with synchronous rectifications on the secondary. Below is the configuration for the DPWMs. Can someone verify the DPWMs below?

DPWM0A = Primary_Forward_MOSFET

DPWM0B = Secondary_Clamp_MOSFET

DPWM1A= Primary_Clamp_MOSFET

DPWM1B = Secondary_Forward_MOSFET

void init_dpwm0_OL(void) // DPWM1B is Used to drive Sync-FET

{

Dpwm0Regs.DPWMCTRL1.bit.GLOBAL_PERIOD_EN = 1;

Dpwm0Regs.DPWMEV1.all = 0; //

Dpwm0Regs.DPWMEV2.all = (PERIOD >> 1);

Dpwm0Regs.DPWMEV3.all = (PERIOD >> 1 ) + DEAD_TIME;

Dpwm0Regs.DPWMEV4.all = PERIOD - DEAD_TIME;

Dpwm0Regs.DPWMCTRL0.bit.PWM_MODE = 0; // Set to normal mode

Dpwm0Regs.DPWMCTRL0.bit.CLA_EN = 1;

Dpwm0Regs.DPWMCTRL1.bit.EVENT_UP_SEL = 1; // Events update at the end of period

Dpwm0Regs.DPWMCTRL1.bit.CHECK_OVERRIDE = 1; // Normally CLA == 0 is considered a fault; Set the check-override so cla==0 is

Dpwm0Regs.DPWMCTRL1.bit.ALL_PHASE_CLK_ENA = 1; // Need all phases for hi Resolution

Dpwm0Regs.DPWMSAMPTRIG1.all = 1500; //(PERIOD >> 1); //2100; 279*16ns = 4.464us;-5000; // Writing to all in order to normalize to high resolution

Dpwm0Regs.DPWMCTRL2.bit.SAMPLE_TRIG_1_EN = 1;

Dpwm0Regs.DPWMCTRL0.bit.PWM_EN = 1;

Dpwm0Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN =0; // DPWm0 is master

Dpwm0Regs.DPWMCTRL0.bit.MASTER_SYNC_CNTL_SEL =0; // DPWm0 is master

//*******************************************************

//Enable Sync Fets

Dpwm0Regs.DPWMCTRL2.bit.IDE_DUTY_B_EN = 1; //enable ide

//*******************************************************

}

void init_dpwm1_OL(void) // DPWM1B is Used to drive Sync-FET

{

Dpwm1Regs.DPWMCTRL0.bit.PWM_EN = 0; //disable locally for init

Dpwm1Regs.DPWMCTRL0.bit.CLA_EN = 1; //default is 1 - use cla

Dpwm1Regs.DPWMPRD.all = PERIOD; // use .all for all values, so that the scaling matches

Dpwm1Regs.DPWMEV4.all = 0; // set EVENT 1 to 0% (start) of period

Dpwm1Regs.DPWMEV3.all = (PERIOD >> 1); // set EVENT 2 to 25% of period

Dpwm1Regs.DPWMEV2.all = (PERIOD >> 1) + DEAD_TIME; // set EVENT 3 to 50% of period

Dpwm1Regs.DPWMEV1.all = PERIOD - DEAD_TIME; // set EVENT 4 to 75% of period

Dpwm1Regs.DPWMCTRL0.bit.D_ENABLE = 1; //Duty Cycle is 1-D

Dpwm1Regs.DPWMCYCADJA.all = DEAD_TIME*2;

Dpwm1Regs.DPWMSAMPTRIG1.all = (PERIOD)/2; //3/4 of period

Dpwm1Regs.DPWMCTRL2.bit.SAMPLE_TRIG_1_EN = 1; //enable 1 sample trigger

Dpwm1Regs.DPWMCTRL1.bit.EVENT_UP_SEL = 1; //update at end of period

Dpwm1Regs.DPWMCTRL0.bit.PWM_MODE = 4; //normal mode (this is NOT the default)

Dpwm1Regs.DPWMCTRL0.bit.PWM_EN = 1; // enable DPWM0 locally

LoopMuxRegs.DPWMMUX.bit.DPWM1_SYNC_SEL = 0;

Dpwm1Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN = 1; // DPWm0 is master, DPWM1 is slave

//*******************************************************

//Enable Sync Fets

Dpwm1Regs.DPWMCTRL2.bit.IDE_DUTY_B_EN = 1; //enable ide

//*******************************************************

}