UCD3138A: DPWM duty more then 100%

Andreas Frühstück

Part Number: UCD3138A

With an UCD3138A a charge pump is operating in a closed loop. For this I use a DPWM module in multi-mode. The duty is to be controlled via a frontend and a filter (PI regulator).

Basically, the regulation of the output voltage works fine and the DPWM changes its duty according to the load resistance at the output.

My problem now is, that the DPWM output signal remains switched on for more than 100% duty sometimes. See screenshot:

Can I prevent that somehow?

DPWM initialization:

DPWMEV1.all                           = (int)(Dpwm1Regs.DPWMPRD * 0.05);
DPWMEV2.all                           = 0;
DPWMEV3.all                           = (int)(Dpwm1Regs.DPWMPRD * 0.05);
DPWMEV4.all                           = 0;
DPWMCTRL0.bit.PWM_MODE                = 2;
DPWMCTRL1.bit.EVENT_UP_SEL            = 0;
DPWMSAMPTRIG1.all                     = (int)(Dpwm1Regs.DPWMPRD * 0.96);
DPWMCTRL2.bit.SAMPLE_TRIG1_OVERSAMPLE = 3;
DPWMCTRL2.bit.SAMPLE_TRIG1_MODE       = 0;
DPWMCTRL2.bit.SAMPLE_TRIG_1_EN        = 1;

Filter initialization:

FILTEROCLPHI.bit.OUTPUT_CLAMP_HIGH = (int)(Dpwm1Regs.DPWMPRD * 0.75);
FILTEROCLPLO.bit.OUTPUT_CLAMP_LOW  = 0;
FILTERCTRL.bit.OUTPUT_MULT_SEL     = 1;
FILTERCTRL.bit.PERIOD_MULT_SEL     = 0;

Can anyone help? Thanks in advance!

over 5 years ago

0 Yitzhak Bolurian over 5 years ago

TI__Mastermind 18370 points

What is the FILTER2_PER_SEL bitfield set to inside the FILTERMUX register?
If it is not set, then the default will be period from DPWM0 and not DPWM2.

0 Andreas Frühstück over 5 years ago in reply to Yitzhak Bolurian

Prodigy 230 points

Thanks for your soon reply! I'm working with FE0, FILTER1 and DPWM1 modules. The LoopMux configuration is:

LoopMuxRegs.SAMPTRIGCTRL.bit.FE0_TRIG_DPWM1_EN = 1;    // Use DPWM1 sample trigger for FE0
LoopMuxRegs.FILTERMUX.bit.FILTER1_FE_SEL       = 0;    // FE0 provides data to CLA1
LoopMuxRegs.FILTERMUX.bit.FILTER1_PER_SEL      = 1;    // CLA1 switching period select from DPWM1
LoopMuxRegs.DPWMMUX.bit.DPWM1_FILTER_SEL       = 1;    // CLA1 is providing input to DPWM1

If the LoopMux will provide the frequency of a wrong DPWM, the duty should exceed 100% oftener! I think, the issue is, that the DPWM module doesn't switch off its output pin after arriving the filters duty. What are possibles reasons for such a behavior?

0 Yitzhak Bolurian over 5 years ago in reply to Andreas Frühstück

TI__Mastermind 18370 points

Plaese set the:
DPWMCTRL1.bit.EVENT_UP_SEL = 1;
and see if the issue is resolved.

Regards,

0 Andreas Frühstück over 5 years ago in reply to Yitzhak Bolurian

Prodigy 230 points

Hello Yitzhak,

thanks for your assistance: this has solved my problem!

Kind regards,

Andy

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UCD3138A: DPWM duty more then 100%