If I interpret the TI UCD92xx errata correctly the maximum slew rate for a specific rail on an UCD9240 would be given by:
That is, if I have a 1.8V rail that uses a divider of 2/3 (resulting in a control voltage of 1.2V), and an AFE gain of 4x.
Is this interpretation correct?
What are the consequences of violating these conditions?
This should be an easy question. Anybody?
The max slew rate during the soft start and soft stop ramps are based on the following table.
max step/100 usec
During the soft start ramp, the controller is calculating a value and updating the setpoint reference DAC every 100 usec. The digital control loop then uses this new value to regulate the output voltage to. To keep the sensed error voltage within the dynamic range of the sampling ADC, each step in the ramp is limited to 75% of the dynamic range.
So, for this example, the fastest the voltage that can be ramped during a soft start or soft stop is (480 mV/msec)*(3/2) = 720mV/msec
Then a 1.8V rail can be brought up no faster than
(1800 mV)*(1 msec / 720 mV) = 2.5 msec
This can be seen by setting the TON_RISE value to 0 and watching a start ramp of Vout on the scope.
Note that trying to ramp any power supply fast means that you are asking it to charge the output capacitance fast, which demands lots of current. The faster the soft start ramp, the more potential there is to generate an over-current fault.
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