We are manufacturing PSU in reasonably large qty and continuously have a "noise problem" where the synch FET gate drive is "spiked" by the rising edge of the voltage on its drain pin. This spike causes us the predictable grief in EMC and output rail "noise" let alone being a reliability issue.
We have tried numerous Qgd/Qgs ratio around 1.5 down to 1.1 and Qgate(tot) around 27nF-50nF - and still have a yield problem. Maybe the answer is to ensure this synch MOSFET ratio is always less than 1 ? or is TI able to state it should be less than 0.80 etc ..
It seems a possibility the manufcaturer - knowing the threshold gate drive capability should be able to specify the Qgate(total) and Qgd/Qgs ratio to ensure correct performance ??
Can anyone help with some experience in this issue ?
My name is Peter James Miller. I am the lead applications engineer for the TPS40k product line. Let me see if I can offer you some insight into what you are seeing and how to address it:
First, MOSFETs contain a number of non-linear parasitic capacitances. As a result of these non-linearities, they are typically characterized by a charge rather than a capacitance. The three of most import during switching are the Gate to Drain charge (Qgd or Miller charge - no, not related to me at all) the Gate to Source Charge (Qgs) and the Drain to Source charge (Coss or Output Capacitance) For the effect that you're describing, we're only conserned about Qgd and Qgs.
Qgs is the charge that must be delievered to the gate-source capacitance to raise the gate-source voltage (Vgs) to the specified level (typically 4.5V)
Qgd is the charge that must be delievered to the gate-drain capacitance to rasie the gate-drain voltage (Vds - Vgs) to the specified level (This will vary from spec to spec a little, but you can calculate it from Vds-Vgs from the test conditions in the MOSFET datasheet)
In a totem pole MOSFET power stage where the is a fixed voltage from the drain of the top or high-side FET to the source of the bottome or low-side FET, when one FET turns ON, the drain-source of the other FET increases rapidly. This rapid increase in drain-source voltage causes current to flow through the parasitic gate-drain and gate-source capacitors.
Typically, when the high-side MOSFET of a totem pole MOSFET pair turns on, the drain-source voltage of the low-side FET increase rapidly and the parasitic gate-drain and gate-source capacitors of the low-side FET form a capacitive divider with equal charge on both capacitors. If Qgd is greater than Qgs, this equal charge forced the gate-source voltage of the low-side FET above the specified voltage, well into the FET's "ON" state unless some of this charge can be removed from the gate. If Qgd is smaller than Qgs, this equal charge forced the gate-source voltage of the low-side FET to less than the specified voltage and the FET is "OFF" to partially on.
It may be necessary to scale Qgd based on differences between the specified Vds-Vgs and the actual operating point, which is typically the full scale voltage of the totem pole.
Ideally, MOSFETs with Qgd < Qgs are selected to minimize the chance of turning on a MOSFET as such, however additional precautions may still be warrented, including:
1) Slowing the rate of rise of the common (switch) node of the totem pole. This allow more time to remove some of the Gate-Drain charge without charging the gate-source capacitance. This can be achieved by added a series gate resistor to the other MOSFET, or in cases of a floating bootstrap drive, adding a resistor in series with the bootstrap capacitor.
2) Improving the ability of the gate-drive to remove charge from the gate during the switching node transition. This can be pretty hard, but typically involved careful attention to layout, eliminating unnecessary path length, loop area or extra resistance in the driver to gate and FET source to driver return paths.
3) Adding additional gate-source charge through external capacitors. Adding a 1nF external capacitor from gate to source of the FET typically adds about 4nC of gate-source charge with about 2nC before the FET reaches its threshold voltage, providing some additional protection, however this requires extremely careful attention to layout since any inductance in the capacitor's loop will impede it's ability to absorb Gate-Drain charge.
Peter James Miller
Power Management - DC/DC Solutions - Industrial & Communications DC Solutions
Member Group Technical Staff 2008
Hi Pete ..thks for the answer ..and yes I know all the theory but this problem is bugging me still ...I have what I consider to be an ideal layout and latest FET trials use an NTD4806 IPAK (Cgd/Cgs=1/3 !) and which states it has a dV/dT rating of 6v/nsec but even if I have a diode resistor thingy slowing the rise time with the series FET and have good snubbing to reduce the ringing - its still a marginal proposition.
I dont like slowing the gate rise on the series FET - increases dissipation, so Im forced to look at something with more grunt as a driver ...or firstly a NPN+diode thingy to enforce the gate OFF signal on the synch FET...Ive never had so much trouble and wonder if batches of the TPS40K have for some reason faulty/weak synch gate drivers ??
I didnt have this trouble with the first batches ....we have used Three batches so far ...
OK batch 88T/E1XT 200pcs
OK batch 62T/D5L3 3K
Suspect ? 74TG4/VCXF 5Kpieces
Can you tell me the decode date/batch algorithmn on the batches Pete ? The / means top line first over bottom line second - the TOP TOP line says TPS40055.
can you send response to email@example.com so I get answers ASAP ?
would be appreciated if you can tell me of major silicon revisions - date codes info ...etc.
We are looking at 100K batch next and at this problem rate Im scared ..nothing screws EMC like shoot thru !!
I pulled up the NTD4806 IPAK datasheet from On-Semi (http://www.onsemi.com/pub_link/Collateral/NTD4806N-D.PDF) and this datasheet shows Qgd = 7nC and Qgs = 7nC when Vgs = 4.5V and Vds = 15V. Since 7nC of charge will drive the gate to 4.5V, the gate must have less than 3.5nC of charge to minimize leakage current and prevent shoot through. At 15V, the gate driver already needs to remove more than 3.5nC of gate charge during the switch node transition and as the peak switch node voltage increases, so does the gate charge requirement on the drive.
I will have to check on the "magic decoder ring" myself as I am not familiar with it myself, though I can tell you the G4 that you've underlined above is a ROHS compliant part.
The only significant silicon revision to the TPS40055 controller was the addition of some test pad to allow testing of certain internal devices during probe to improve quality
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with respect to these materials. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.