Hello,
I use the Halfbridge driver TPS28225 to drive tow Mosfets from Fairchild (FDS6612A) at a Frequency of 2MHz. Because the fast rise and fall times I have some problems with oscillation at freqencies around 160Mhz. So it is not posible to get the halfbridge to work at 24V bridge voltage because the FET's get quite hot.
After some tests with damping the oscillation of the halfbridge output I wanted to have a try with reducing the rise and fall times by putting a resistance between driver output and gate of the MOSFETs.
My question is now, can I get problems whith the "Dead-Time Control" of the TPS28225 if I do this?
Thanks for the help
I wanted to have a try with reducing the rise and fall times by putting a resistance between driver output and gate of the MOSFETs.
Adding resistance in series with the gate-drivers will not reduce the rise and fall times. Adding resistance in series with the MOSFETs will increase the rise and fall-times by increasing the series resistance and reduce the available current to drive the MOSFET gate charges. Typically, reducing rise and fall times will make oscillations worse as faster transients are forced on circuit parasitics.
Adding resistance to increase rise and fall times (reduce slew rates) may reduce the oscillations. Typically resistance is added in series with the bootstrap capacitor powering the high-side (floating) driver. This increases the pull-up resistance of the drive and thus slows the rising edge. This will not impact the dead-time control circuit and should reduce any ringing on the leading edge of the switching node.
Adding even small resistances in series with the gate drives can adversely affect the dead-time control. Since dead-time control is monitoring the gate drive voltages at the gate-drive output pins, adding series resistance will cause the driver to sense that the external MOSFET is "OFF" before the MOSFET has actually turned off. This is why the resistor in series with the bootstrap capacitor is prefered.
Do not add a resistor in series with the VDD pin to attempt to slow the low-side FET driver as this will cause increased ripple inside the IC and could interfer with the input threshold and logic circuitry.
If you truly want to reduce the rise / fall times, you will need to select MOSFETs with smaller gate charges, but this will likely increasing ringing rather than decrease it.
There is a diode based clamping circuit that uses a small (0.1uF) capacitor as close to the MOSFETs Drain/Source (Drain of high-side Source of low-side) and a pair of diodes from SW to the drain of the high-side and from the source of the low-side to the SW pin that can help clamp switching node ringing. This only slightly reduces the amplitude but does greatly improve the duration of the rining. To be effective the path inductance must be kept extremely low so very small devices need to be used with very tight layouts.
It is not the strongest of the species that survives, nor the most intelligent that survives. It is the one that is the most adaptable to change. - Charles Darwin
Hello Nancy,
thank you for your helpful recommendations. I did not try them at the moment but I'm shure they will work out.
Just some Questions to your recommendations.
1. Do you mean a circuit like this?
2. what kind of diodes do you recommend? Shotkey diodes for higher Currents?
Thanks for your help again, Martin
P.S.: Off course with adding the resistance I wanted to increase the rise time of the driver ;-)
Hi Martin,
Yes, that is the circuit configuration, but what is critical in the loop inductance. The TPS28225's dead-times are short enough that the ground to SW diode shouldn't carry much average current (less than 2 25ns pulses per switching cycle) and the high-side diode will only carry the ringing energy. Typically, smaller packaged small signal diodes provide better clamping due to there faster response time. The low-side diode may need to be slightly larger since it may carry the full load current for a few nano-seconds each switching cycle.
I can not stress enough that it is layout that is critical. The goal is to provide a very low impedance path to clamp the switch node ringing. This means using small packages and very tight layout practices, avoiding vias if possible. If you have to use vias to make the connection due to board contraints, use 2 vias in parallel to minimize inductance.
Regards,
nancy!