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TL431 - stable and unstable

Hirotaka Matsumoto
Guru 27525 points
Other Parts Discussed in Thread: TL431, TINA-TI

Hi all

Would you mind if we ask TL431?

<Question1>
On the datasheet P16, does "unstable" mean that there is no enought phase margin?

<Question2>
In relation to <Question1>, do you have the blod plot data?

Kind regards,

Hirotaka Matsumoto

  • 0
    TI__Mastermind 24485 points

    Hello Matsumoto-san,

    1. You are correct, unstable means that there is not enough phase margin. The boundary denotes 0 or close to 0 phase margin.

    2. We do not have the bode plots available, however, because the boundary is 0 phase margin, we typically recommend designing at least 1 decade away from the boundary to be stable across temperature and process. 

    Additionally, please refer to the following application note for additional details. This app note also provides a graph showing where the stability has 30degrees of phase margin to help design.

    http://www.ti.com/lit/an/slva482a/slva482a.pdf

    Best,
    Michael

  • 0 in reply to Michael J Schultis
    Guru 27525 points

    Michael san

    Thank you for your reply always!

    We have some additional questions as follows;

    <Additional question1>
    "This app note also provides a graph showing where the stability has 30degrees of phase margin to help design."
    ->Our customer would like to have 45degrees phase margin.So, could you let us know Stability Boundary Conditions like as app note?

    <Additional question2>
    We could not find ESR discription for the stability on the app note.
    Do you have the stability characteristic diagram with ESR vs CL(Load capacitiance - uF)?

    Kind regards,

    Hirtotaka Matsumoto

  • 0 in reply to Hirotaka Matsumoto
    Guru 27525 points

    Michael san

    And then, our customer would like to simulation to confirm phase margin using TINA-TI.
    We sent you files using private message.(Because this design inculdes confidential(customer's circuit) content.)
    So, could you give us the some advice?

    We need your help.

    Kind regards,

    Hirotaka Matsumoto

  • 0 in reply to Hirotaka Matsumoto
    Guru 27525 points

    Michael san and team

    We are sorry to rush you, however could you let us the advice?  

    Kind regards,

    Hirotaka Matsumoto

  • 0 in reply to Hirotaka Matsumoto
    TI__Mastermind 24485 points

    Hello Matsumoto-san,

    1) Unfortunately, we do not have the bode plot data to show for 45degrees phase margin. To maximize the margin while having capacitance on the cathode, I suggest >10uF of capacitance, and the more the better.

    2) I am not sure i understand the question. Are you looking for an additional ESR graph that shows 45degrees phase margin? All the data that we have provided in Figures 5-8 in the application note is what we have. http://www.ti.com/lit/an/slva482a/slva482a.pdf

    The additional ESR will help with stability, but knowing exactly what the phase margin will be would require a bench test.

    Best,
    Michael