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Part Number: TPS62067
We are required to design the voltage monitor mechanism that meets below illustration. Currently, the PGOOD signal is used for power sequence and also false detect. But for most of the application the minimum detection voltage will less than operation voltage range, thus violate the rule. For example, the TPS62067 has PGOOD falling threshold typ. 90%, not suitable for 5% tolerance application.
The question is:
For application with low voltage tolerance, (5%, for example) what will be the solution choice? Is there a power IC with high sensitive PGOOD signal or I should choose another power monitor IC?
For the standalone monitor IC, please help to give some suggestion. Please see below spec:
(a) 4 input, variable voltage detection range should include 1.2V~3.6V, tolerance target to +/- 1%.
(b)1 input, variable voltage detection range should include 3V~3.6V, tolerance target to +/- 2%.
my pleasure to support you.
I have some questions:
-do you need to detect a DC voltage fall, or do you need also to detect AC events that fall outside the +-5% tolerance window?
-Do you define this a fault because the 5% is the voltage tolerance of the load?
-has your application heavy load transients?
The internal PG of this device (and many other) are not built for a precise detection of load's input voltage tolerances, that's why the threshold is set to 90%, and the detection is relatively slow. Their purpose is rather to detect a general "no voltage" fault, or for sequencing purposes.
If you need to be really strict on the voltage supervision, in terms of accuracy and bandwidth, I can't suggest anything but a voltage supervisor. TPS3702 is a good example. I would suggest you to open a dedicated post on the TPS3702, so that the right person for these kind of products will give you a deeper support.
Thanks and best regards,
Find answers to common questions in the LPDC App Note Index
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In reply to Emmanuel Granatello:
Thanks for help.
About your questions below:
[Customer] It should be able to detect both DC and AC events that fall outside the tolerance window.
[Customer] Yes. I just found I miss to attach the picture. Please see below, the monitor detection range should not overlap the normal power IC operational output range, but also has to within the load voltage range.
For example, assume a DDR power rail may requires +/- 5% tolerance and a Power IC set to center with output +/- 2.5% tolerance. This leaves the monitor with maximum tolerance +/-1.25%. This is how I get the target tolerance for the monitor IC.
[Customer] Yes, heavy load transients may happen. They are for core power such as CPU and DDR.
We would like to learn more about the voltage monitor. Customer might need to monitor 3~4 voltage rails with typical voltage(1.2V, 1.35V, 1.8V, 3,3V). We found TPS3702 is a good choice that no need to add external resistance. However it doesn’t support 1.35V rail monitoring and adding 3~5 monitor ICs also takes a lot PCB size. Do you think TPS386000 is a good choice?
In reply to Ian Wang:
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