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TPS65910 start-up problem(Errata?)

Other Parts Discussed in Thread: TPS65910

Hi,

We have an issue with the TPS65910A31 start-up,
the TPS65910x is used as a PMIC for AM335x and out of 5 custom boards 3
are not working properly. During power up the VRTC voltage is very low at 0.8V.

After some testing and with the help of the below E2E we found that
the problem was related to the capacitor value on VRTC pin.

Even the below E2E mentions that After lots of debugging I found that
if we change capacitor value on VRTC pin to 0.1uF all the boards were working perfectly fine.
e2e.ti.com/.../320847

But as per the TPSxx datasheet, the capacitor value for VTRC should be in
the range of 0.8uF to 2.64uF.

In our case out of 3 boards

1> Board 1 works if we change the  VRTC capacitor value from 2.2uF to 0.1uF
2> Board 2 works only if we remove the VRTC capacitor
3> Board 3 doesn't work at all.

Is this some kind of Errata of this device?

Best Regards
Kummi

  • Any suggestions on this issue?
  • Hi Kummi,

    This is not expected behavior, are there any loads connected to VRTC other than the capacitor?

    Can we also confirm the power pad is properly grounded?
  • Hi Richard,

    Thank you so much for the information.

    Yes we believe this is not an expected behavior, but we have 2 Good boards
    and 3 bad boards. And the PCB is designed by our experienced OEM who have successfully
    designed many AM335x+TPS65910 applications till now.

    The VRTC is connected to BOOT1 of the TPSxx and VDDS_RTC and RTC_KALDO_ENn of AM335x.
    And we have cross checked the Power PAD is properly grounded.

    Is there any other troubleshooting points to find out the root cause?
    As mentioned above even other customers have the same problem with this IC,
    it seems 7 out of 25 boards had this VRTC issue.

    Best Regards
    Kummi
  • This could occur if the input supply dips low enough to transition the PMIC into BACKUP state, is that applicable to your application?

    Discussion on this topic can be seen here: e2e.ti.com/.../222327

    The VRTC LDO can current limit itself in the BACKUP state for all TPS65910x devices, and since this LDO provides internal blocks it must be allowed to regulate to the proper 1.8V. If removing the VDDS_RTC connection fixes this issue I would start there.

  • Hi Richard,

    Thank you for the suggestions.
    I am sorry for the delay.

    The input supply seems to be OK and we believe the IC is not in BACKUP state.
    I think this scenario doesn't apply to this application.

    With regards to removing the VDDS_RTC connection, removing this connection
    seems difficult because we have to cut the PCB to do that.

    With regards to the VBACKUP pin even though we are not using the BACKUP supply,
    VBACKUP is connected to 4.7uF capacitor. Does this effect the proper working of the PMIC?





    Best Regards
    Kummi

  • Hi Kummi,

    Your configuration will work fine during normal operation. Can you capture oscilloscope shots of VRTC and VREF to demonstrate the difference between the 3 boards?

    For now, the easiest thing to do is drop the VRTC capacitance towards the lower values to reduce the current demand on that regulator during start-up. If VDDS_VRTC is not needed from the PMIC, I would recommend disconnecting it from in future revisions.

    The customer should try to ensure VRTC is not being used as a logic input if unnecessary to reduce the likelihood of overloading the LDO.
  • Hi Richard,

    Thank you.

    Below are the oscilloscope shots of VRTC and VREF during power up.
    Ch1(Yellow)-VRTC (500mV/div settings)
    Ch2(Blue)- VREF  (500mV/div settings)
    Ch3(Purrple)- Input voltage(VCC1 to VCC7) (2V/div)

    Board 1 (Working after VRTC Capacitor change)

    Board 2 (Working after VRTC Capacitor change)

    Board 3 (Not working)


    Best Regards
    Kummi

  • Hi Kummi,

    Those rails look fairly noisy, do we know if that is caused by coupling from the probe ground loop or if that is legitimate noise on the VRTC and VREF rails?

    Does the REFGND have a dedicated trace to the device and reference cap, or are they both shorted to a PGND?

  • Hi Richard,

    Thank you for the comment.

    The noise was because of the probe and the rail looks normal after shortening the ground cable.

    With regards to your suggestion on reducing the VRTC capacitance towards the lower values,
    As per the TPS65910 datasheet the Min Value is "0.8uF" and preferred value is "2.2uF".
    Is it OK to use very small values like "0.1uF", will it be an unrecommended value from TI?

    Best Regards
    Kummi
  • Hi Richard,

    I forgot to answer about the REFGND connection.
    The REFGND is connected to the Main Ground Net (DGND) similar to the AM335x EVM or StarterKit.


    Best Regards
    Kummi

  • Hi Richard,

    Could you please let us know about your comments
    with regards to reducing the VRTC capacitance.

    As per your suggestion on reducing the VRTC capacitance towards the lower values,
    As per the TPS65910 datasheet the Min Value is "0.8uF" and preferred value is "2.2uF".
    Is it OK to use very small values like "0.1uF", will it be an unrecommended value from TI?

    We believe this is the only option left.

    Best Regards
    Kummi
  • Hi Kummi,


    It is simply not recommended to use values lower than those listed in the recommended operation conditions.

    A different output cap value might address this single issue, but could also compromise the loop stability of the LDO during normal operation. The best solution is to ensure that the load on the VRTC LDO is less than 100uA before VCC7 has surpassed ~2.8V.

  • Hi Richard,

    Thank you so much for the reply.
    And I am sorry for the delay.

    Actually the custom board is using TPS65910A31A1
    and as you know in this device the VRTC LDO will be in full power when in
    OFF mode and does not need an external regulator.
    I believe the  VRTC LDO won't be less than 100uA during power up even if
    it goes to Low power mode.

    Even the User guide(SWCU093D) has VDDS_RTC connected to VRTC as shown below.


    As per this E2E conclusion can we assume there is a possibility that
    during power up, VRTC LDO may go into the low power mode with less than 100uA output current?

    Best Regards
    Kummi

  • Hi Richard,

    With regards to your solution,
    "best solution is to ensure that the load on the VRTC LDO is less than 100uA before VCC7 has surpassed ~2.8V."

    Could you please let us know if there is any reference schematics to implement the above?
    according to my understanding the only way is to use external regulator for VDDS_RTC.

    Best Regards
    Kummi
  • Hi Kummi,


    If all other loads have been removed from the VRTC LDO, and the LDO is still unable to reach 1.8V, then an external regulator would be the next most common solution.

    One could also use an external switch circuit to initially isolate loads from VRTC, but this may not be acceptable for all applications and there is no application schematic available for such an implementation.

  • Hi Richard,

    Thank you so much for the suggestion.
    After some research we have found one solution.

    As per your suggestion to ensure that the load on the VRTC LDO is less than 100uA during start-up,
    we have modified the schematics, we removed the connection between VTRC LDO and VDDS_RTC.
    And connected the VDAC to VDDS_RTC and RTC_KALDO_ENn.




    The Custom board seems to be working with this connection,
    but we are not sure if this a proper connection.
    Could you please let us know if this kind of connection is allowed with TPS65910.

    Best Regards
    Kummi

  • Hi Kummi,

    This is fine from the PMIC perspective. Please remember there is also an RTC within the TPS65910 that can be utilized if RTC is still needed when VDAC is disabled.