LMG5200: Ringing at 3 MHz in my LMG5200. Not expected in simulations

Part Number: LMG5200

Hi,

I have developed a first prototype for my final master thesis using the LMG5200. I have simulated it in Tina and I dont see the ringing. I guess it is due to the layout and the EMI.

Data that is missing in my pics:

- The bootstrap cap is 0.15uF and X7R.

- The resistor and capacitors of HI and LI is 0 ohms and 10pF respectively.

- I am generating the PWM inputs with dead times through a zybo from diligent.

It is working, however I am seeing a big ringing above 1MHz. What may be the reason of this ringing? I attach you 3 pics: 

- Top layer of my pcb

-Bottom layer of my pcb

- Picture of the ringing seen in the osciloscope (purple curve)

Thank you very much in advance,

Carlos Salto

  • Hi, Carlos,

    Thanks for your interest in our products.

    I suspect the problem is the decoupling on the VIN node. It appears all the capacitors are on the bottom of the board which will result in significant inductance.

    Check out the layout of the EVM: www.ti.com/.../snva729a.pdf

    The layers of the EVM are also shown in a zip file in the Product Folder so you can better see them.

    I suggest trying to improve the decoupling and see if that reduces the ringing.

    Let us know what you find. If this fixes the issue, please press the "Verify Answer" button.

    -----

    Don Dapkus

    GaN Systems and Applications Engineering Manager

    Dallas, TX USA

  • In reply to Don Dapkus:

    Hi Don,

    First of all thank you for the fast response.

    The problem is that the layout considerations are thought for a multilayer PCB design, however at my university we only have the possibility to do a 2 layer design. I have done my design based on the datasheet of the LMG5200. I attach a capture of the guide I have followed.

    I know that in the datasheet it is said that 2 layer PCB are not recommended due to the power loop inductance, however is the only way we have to do it.

    Thats the reason all my decoupling caps are on the bottom layer.

    I am also aware that the FR4 pcb is 1.57mm which is much more than the recommended 5 mils in the layout considerations, which again increases the power loop inductance.

    Having those layout limitations, Is there anything else I could do to improve the ringing I see?

    Thank you very much for your time and quick response again,

    Carlos Salto

  • In reply to Carlos Salto26:

    Hi, Carlos,

    That's a tough one... You might see some improvement by scraping off the soldermask on the top of the board and soldering some ceramic capacitors there.

    Based on the diagrams, I think this is possible?

    -----

    Don Dapkus

    GaN Systems and Applications Engineering Manager

    Dallas, TX USA

  • In reply to Don Dapkus:

    Hi Don, 

    I think that may be possible. I will try it tomorrow.

    I was also thinking of buying a thinner pcb FR4 (I found one 3 times thinner) and implement the layout there, so the inductance reduces a 66%. Do you think that would work?

    I have also changed my design to work at 2MHz instead of 3MHz, which again I think will reduce the impedance in 33%. And I am hoping that the combination of the 3 ideas will reduce significantly the power loop inductance.

    Thank you very much again for the fast responce and for your time,

    Carlos Salto 

  • In reply to Carlos Salto26:

    Hi, Carlos,

    Did you get a chance to try this? Any improvement?

    -----

    Don Dapkus

    GaN Systems and Applications Engineering Manager

    Dallas, TX USA

  • In reply to Don Dapkus:

    Hi Don,

    After the modifications done we saw around a 50% improvement, which is quite good and I think is the best we can get using 2 layers.If you have any other idea please tell me.

    Thank you verymuch for your time and interest, I attach you a picture of the new waveform obtained,

    Carlos Salto

  • In reply to Carlos Salto26:

    Hi, Carlos,

    I'm glad it improved considerably! One other thing you might try is different value capacitors (smaller ones) to get a lower effective impedance at the frequency of interest. Larger caps have too much ESL which makes them less effective at high frequencies.

    Good luck on your project!

    -----

    Don Dapkus

    GaN Systems and Applications Engineering Manager

    Dallas, TX USA

  • In reply to Don Dapkus:

    Hi Don,

    Although it has improved we are thinking of doing a multilayer PCB now (the peak is still too big).

    Is it possible to get an example of a multilayer layout so we can modify it to fix our project? (we are using kicad to design the layout).

    As we can only send one prototype to manufacture (it has to be done in an external bussines), it is desirable that the this prototype is the best possible, thats why we would really appreciate having your layout sample.

    Thank you very much again for all your time,

    Carlos Salto
  • In reply to Carlos Salto26:

    Hi, Carlos,

    The files are posted on our website at:

    www.ti.com/.../getliterature.tsp

    Let me know if you need anything else!

    -----

    Don Dapkus

    GaN Systems and Applications Engineering Manager

    Dallas, TX USA