Part Number: LM5113
One good solution to mitigate ring/oscillation with GaN FETs is using a negative gate bias (-3V) for turn-off. You have devices that accomplish this (LM5110), however, I strongly desire the half-bridge driving capability of the LM5113.
Is it possible to configure the LM5113 to drive with a negative gate bias? For example, could I simply just lower the ground potential of the gate driver 3V relative to the half-bridge ground, essentially treating the "GND" pin on the LM5113 as a "VEE"
Appreciate the support!
I have a couple of points I would like to draw your attention to before attempting to separate the grounds:
1. Separating the two voltages, it would make the gate loop inductance a lot larger, which might defeat the purpose as you would most likely experience an increase in the ground bounce.
2.Whatever negative ringing you would get on the gate , is pushed further negative by this bias,which leaves a smaller margin to the negative abs-max for the Vgs.
The preferred ways to mitigate gate ringing/ accidental turn-on are:
1. Design the gate loop as small as possible, by using microvias and a layer2 return with a layer-to-layer spacing of less than 5mils, you can get 3-5nH of inductance, which reduces the ringing
2.add some resistance to dampen out the LC and slow down the slew rates slightly
3.if the miller ratio is unfavorable, you can add some small capacitance from gate to source (generally this is not a preferred option!)
In reply to Alberto Doronzo:
Both are very good considerations to make. My hopes that there was a half-bridge driver equivalent to the LM5110.
In reply to Joel Barker:
The GaN devices we are using has an Rds(on) value that is dependent on the gate drive voltage. So, when driving it at 6V we get a better Rds(on) value (~7% better than 5V).
When the LM5113 is supplied with 6V, the lowside outputs 6V to the gate, but the bootstrap clamps the high side driver at 5.2V.. is there a way around this?
Thanks again for all your help!
I want to start with reminding you that connecting 6V to Vdd is above the recommended operating condition maximum of 5.5V.
Operating at higher voltages might affect operation and lifetime and any assurance on the part (i.e. you are operating it outside specifications).
Now, if you want to experiment with a higher voltage my recommendation would be to use an external schottky diode to bootsrap Vdd to HB, and add an LDO clamp in series after the diode, to limit the voltage seen by the HB cap to whichever level you decide to select.
If you do not want to add an LDO, a zener clamp across HB would provide similar protection. In this case you would have to add a 2-5ohm resistor in series with the bootstrap diode to limit peaks.
please see below. In red is what you would need to add. Either the LDO or the zener (and add a resistor in series with the schottky).
I've tried your recommendation, however, despite my efforts I can not get the high side to drive above 5.2V.. I attached an image of one of the simulations I have done.
I will look into this and answer to you shortly.
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