Hi ! I'm using TPS53632G to design a half-bridge converter. The parameters: VIN=36-75V, VO=28V, IO=10A. I 'd like to ask you a few questions about the data sheet（Revision A ） during the design process.
1、7.4.1 and 7.5.7 on the discussion of single and multip phase, how to understand the problem of multip phase? Which pin is CSP3?
During single-phase operation, every SW_CLK signal generates a switching pulse on the same phase. Also, ISUM
voltage corresponds to a single-phase inductor current only.
During multi-phase operation, the controller distributes the SW_CLK signal to each of the phases in a cycle.
Using the summed inductor current and cyclically distributing the ON pulses to each phase automatically gives
the required interleaving of 360/n, where n is the number of phases.——7.4.1
7.5.7 Active Phases
Normally, the controller is configured to operate in 3-phase mode. To enable 2-phase mode, tie the CSP3 pin to
a 3.3-V supply and the CSN3 pin to GND. To enable 1-phase mode, tie the CSP2 and CSP3 pins to a 3.3-V
supply and tie the CSN2 and CSN3 pins to GND.——7.5.7
2 Overvoltage Protection
In7.3.7，7.3.7 Overvoltage Protection
An OVP condition is detected when the output voltage is greater than the PGDH voltage, and greater than VDAC.
VOUT > + VPGDH greater than VDAC. In this case, the converter sets PGOOD inactive, and turns ON the drive for
the low-side MOSFET. The converter remains in this state until the device is reset by cycling the V5A, VDD or
VINTF pin. However, the OVP threshold is blanked much of the time. In order to provide protection to the
processor 100% of the time, there is a second OVP level fixed at VOVPH which is always active. If the fixed OVP
condition is detected, the PGOOD are forced inactive and the low-side MOSFETs are tuned ON. The converter
remains in this state until the V5A, VDD or VINTF pin is reset.——7.3.7
What do the VPGDH and VOVPH mentioned in the article refer to? How does overvoltage protection detect and work?
In the 6.5 Electrical characteristic:
| PROTECTION: OVP, UVP, PGOOD AND THERMAL SHUTDOWN | ||||
| VOVPH | Fixed OVP voltage | VCSN1 > VOVPH for 1 µs | 1.60 1.70 1.80 | V |
| VPGDH | PGOOD high threshold | Measured at the VFB pin w/r/t VID code, device latches OFF |
190 245 | mV |
| VPGDL | PGOOD low threshold | Measured at the VFB pin w/r/t VID code, device latches OFF |
-348 -280 |
How do you understand these parameters? Overvoltage protection is detected by CSN1 ? When CSN1's voltage is greater than 1.7 V(VOVPH voltage? ),the Overvoltage protection occurred? If so, how can the current be detected in this design? Because the CSN1 pin is connected to VO, and VO = 28V, how should current detection be configured?
3 CURRENT SENSING
If resistor sensing is used, is a small resistor directly connected behind the output filter inductor to be detected without NTC thermistors compensation?
If the secondary uses full-wave rectifier, how should the current sampling be configured? How to use CSP1, CSN1 and CSP2, CSN2?
4 In 8.2.1.2.7,EQUATION 14, what is the RLL?
8.2.1.2.7 Step 7: Set the Load-Line Slope
The load-line slope is set by resistor, RDROOP (between the DROOP pin and the COMP pin) and resistor RCOMP
(between the COMP pin and the VREF pin). The gain of the DROOP amplifier (ADROOP) is calculated in
Equation 14.
