Working on 800W resonant mode converter with UCC25600 LLC controller.Build up as the typical application diagram and by use of the design tool.It work perfect in steady state (same output current, same load) and Eff. shows up to 95 % close to max load.But with transient loads something strange happens.The Upper fet is blowing even at very light loads. So changing from load to no load which means that the converter goes into burst mode damage the fet. (FCPF22N60)
Can this be caused by the high drain current when gate turns on again after the burst break?
I did'nt quite hit the Lr calculated in the spreadsheet 31uH but ended up with aLeakage induction Lr at about 22UH.
Here is the input parameters used in the spreadsheet.
Vin Min: 375V
Vin Max: 410V
Fsw norm.: 134khz
Fsw Max.: 350khz
Fsw Min : 65khz
Max. Power Limit: 800W
Max. Output Power: 775W
Full load eff: .92
I've designed a LLC with almost the same specs ;-)
Power: 800W outputNon-isolated: 85-264VAC (PFC UC28061) to 400VDC.Isolated: 400VDC to +/- 82VDC (165VDC from + to -) (LLC). Unregulated!fsw = 100kHz.I managed to get 510W out due to the lack of load resistors. I got around 97% efficiency for the LLC alone and total above 93% with the PFC in front at 500W out and 230VAC in.
1) Use a IR2110 gate driver for the MOSFETs.
2) Make sure you don't get a short through your MOSFETs when switching! Increase the dead time to 300ns by adjusting the resistor and measure the two gate signals at different loads.
3) Measure the current in the Lr. Is it correct regarding your calculations?
4) Is your output capacity high enough? Try increasing the uH.
5) Make sure you're running on the resonans frequency when at max load since this is the opimum point.
It could also be your regulation.
I used STW25NM500 MOSFETs.
If you miss your leakage inductance your must insert a Lr of the rest value.E.g.: Total resonance inductance required at operation point (f_sw = f_resonance) = 10uH.
If your leakage is measure to be 4uH, then your should insert a Lr of 6uH to total get 10uH resonance inductance.
I coupled my circuit as shown:
With split resonance capacitors.
Thanks for your reply.
There's some good leads I will try to follow.
I use a gate drive transformer, but it should't make the big difference as long as it doesn't cross conduct. I'll try to increase the dt to 300nsec. and see what happens.
But the Lr value is probably the key to this problem. I'll do some test with this value and at the same time measure the current, pulse by pulse in the upper fet.
Does it work?
Yes it works just fine now.
I took out 830W yesterday without any problem, instability or so.
Burstmode is also working very well now. I change from transformer gate driving to FAN7390 high/low side driver, which seems to work better in burstmode.
So everything is "cool" right now.
Thanks for your feedback to my problem which was very usefull.
You're welcome :-)
What is your efficiency?
By measuring the voltage in the half bridge node (between the two MOSFETs) and measuring the two gate at the same time, so can see if your Lm is OK and that you're in ZVS all the time --> Your deadtime must be larger than the time it takes to V_halfbridge to go to zero.
Press "Verified Answer" if everything is ok now.
Btw. I used a gate driver transformer and couldn't make the LLC work. Switched to IR2110 and everything was fine :-D
Eff. is around 95% which is ok for lab model. I haven't selected diode and fets for Fvd and Rds_on.
My Ln ratio (Lm/Lr) 4.2 might be to low, but I'll check the ZVS/ZCS. I still have the 350nsec deadtime to reduce if there is a margin.
Very nice efficiency since your ratio is low. I assume you're regulating on your output voltage via an opto coupler?
I had a ratio of about 90 because it wasn't regulating. As I recall from the TI seminar 2010/2011, they recommend around 8-9 is you're regulating.
Yes i'm in regulation with an output between 20V and 150V and current 0 - 10 Amps (limited by the max power).
Output is acually very well regulated only few mV change with load changes. In burst-mode the voltage increase a few 100 mV which is Ok for this application.
Regarding deadtime it is a trade-off between light loads and heavy loads so I thing i will stay in the mid zone.
Eff. is poor in the low voltage end because of the Fwd o.m.a. I consider to try and SR solution.
I'm glad I could help.
Yes Sync Rectification on the secondady side would help a lot at high current loads.
Please, with due regards to Mr. FINN, refer to my design and assist me further for prototyping hi-efficiency 500W 650VA LLC HALF BRIDGE STEP-UP DC-DC CONVERTER with fsw 60kHz.
Pl, assist me to complete my design.
I've been reading these threads for a while - great info out there!
I was wondering if anyone knows what the difference is between "Maximum Output Power (Pout)" vs "Maximum Power Limit (Plimit)" as defined in the Design Tool calculator?
Hello Mr Wilson,
I'm new arround this community and PS designing also.
Can you detail a little bit more your design (schematic, transformer core type, output voltage.....)?
I've downloaded the spreadsheet and my Cs, Rs, Rp, Cp values are not valid (name??).
My input data is
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