Part Number: UCC27525
I am experiencing excessive output jitter from a UCC27525D dual MOSFET driver:
I have built a test circuit to explore this problem in its most basic form and it would appear that it is attributable to unexpected operation of the device itself.
The test circuit I used to examine this consists of a UCC27525D supplied from a 13V bench supply and with 10nF, 100nF and 10uF parallel power supply decoupling capacitors in close proximity to the device power pins and with good connections directly to the device ground/power pins (pin 3 and pin 6 respectively). A 3V square wave is injected into the non-inverting driver input pin (pin 4) via a short coaxial cable terminated in 51R directly at the test device. The input (pin 4) and output (pin 5) are monitored using a high-performance 1GHz bandwitdth oscilloscope (Agilent 9000 series) with locally earthed oscilloscope probes. The enables (pin 1 & pin 8) and unused inverting input (pin 2) to the device are left open circuit. There is no load other than the oscilloscope probe on the output being monitored.
The oscilloscope screen shots below were captured with colour grade enabled on the oscilloscope. This clearly shows a quantised varying delay (jitter) on both rising and falling output edges with respect to the associated input transition. These delays alternate each cycle between the two discrete delays.
It should be noted that this jitter effect starts to occur for input waveforms exceeding approximately 1MHz and varies in magnitude with the frequency of the input waveform.
TOP Trace = Input (Pin 4), BOTTOM Trace = Output (pin 5)
Any advice you can give to help resolve this problem would be very much appreciated.
In reply to Stuart Harley:
In reply to Mateo Begue:
My manager is pushing me very hard now for an update. Please can you tell me if you have been able to replicate the problem at your end?
Hi Stuart, How much jitter are you measuring? It looks like 2.5ns on the rising edge and between 1-2ns for the falling edge? How much jitter is allowed for your application? I am still working on replicating your setup. Regards,Mateo
Hi Stuart, I was able to test the UCC27525 under similar conditions at frequencies of 100Hz, 100kHz, and 1MHz.
OUTB rising with INB @1MHz
OUTB falling with INB @1MHz
I noticed some degree of jitter at all three frequencies. Propagation delay of the UCC27525 has a maximum of 23ns. The jitter is within 10% of the propagation delay and should be fine for most applications. What is your application?regards,Mateo
Thanks, you do seem to have been able to reproduce the jitter issue that I see.
Our application requires significantly lower jitter (ideal ~200ps). As you will have observed, the jitter is systematic in nature, with the delay increasing and decreasing on alternate cycles. This is particularly unexpected and very detrimental to our application. I would have though that such behaviour should be indicated in the data sheet for the device.
Do you know the route cause of the jitter? The systematic nature appears to indicate some digital control issue, for instance I note in the data sheet that there is a pulse generated internally to drive the high side N -channel MOSFET in order to speed up the rising edge. Could it be that there is a design/manufacturing problem causing this aspect of the device to introduce jitter in both edges.
Typical delays specified for this device are 13ns (claimed in the data sheet to be "best in class") with 1ns matching between both channels. From this level of spec. I would not expect to see jitters in the order of 3ns which is significantly higher than the specified matching between channels. Can you confirm that the jitter is synchronised between the two channels, or are both channels behaving independently?
In the data sheet you have plots of delay time vs temperature which show ~ 1.5ns variation for a 50 deg C change. However, the jitter swamps this variation. It therefore seems highly unlikely that such significant jitter was not observed during the development of the device. Is it possible that the jitter has been introduced by a manufacturing/design change?
The following claim is also made in the data sheet: "The UCC2752x driver devices feature a best in class, 13-ns (typical) propagation delay between input and output which goes to offer the lowest level of pulse-transmission distortion available in the industry for high frequency switching applications". With such a high level of jitter the pulse width distortion would be significant which is not what would be expected from the data sheet claim.
I would be most grateful if you could urgently investigate the route cause of the jitter and advise if changes to the device will be made to overcome the problem.
Are you aware of an alternative pin compatible part that I could try in the short term?
Hi Stuart, I met with my team regarding this issue. We are looking back at the IC design and running simulations to determine the root cause of the jitter. I will update you when we complete the reviews and simulations. Regards,Mateo
Do you have any news on the investigation into the jitter issue?
Gate Driver Applications Engineering Manager
Dallas, TX USA
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