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800W resonant converter using UCC25600

Other Parts Discussed in Thread: UCC25600

Hi

Working on 800W resonant mode converter with UCC25600 LLC controller.
Build up as the typical application diagram and by use of the design tool.
It work perfect in steady state (same output current, same load) and Eff. shows up to 95 % close to max load.
But with transient loads something strange happens.The Upper fet is blowing  even at very light loads. So changing
from load to no load which means that the converter goes into burst mode damage the fet. (FCPF22N60)

Can this be caused by the high drain current when gate turns on again after the burst break?

I did'nt quite hit the Lr calculated in the spreadsheet 31uH but ended up with a
Leakage induction Lr at about 22UH.


Here is the input parameters used in the spreadsheet.

 

Vin Min: 375V

Vin Max: 410V

Fsw norm.: 134khz

Fsw Max.: 350khz

Fsw Min : 65khz

Max. Power Limit: 800W

Max. Output Power: 775W

Full load eff: .92

Vo: 155V

M: 9

Qr:0.5

Tss:25msec

Td: 200nsec

 

 

 

Br

 

Finn

  • I've designed a LLC with almost the same specs ;-)

    Power: 800W output
    Non-isolated: 85-264VAC (PFC UC28061) to 400VDC.
    Isolated: 400VDC to +/- 82VDC (165VDC from + to -) (LLC). Unregulated!
    fsw = 100kHz.
    I managed to get 510W out due to the lack of load resistors. I got around 97% efficiency for the LLC alone and total above 93% with the PFC in front at 500W out and 230VAC in.

    1) Use a IR2110 gate driver for the MOSFETs.

    2) Make sure you don't get a short through your MOSFETs when switching! Increase the dead time to 300ns by adjusting the resistor and measure the two gate signals at different loads.

    3) Measure the current in the Lr. Is it correct regarding your calculations?

    4) Is your output capacity high enough? Try increasing the uH.

    5) Make sure you're running on the resonans frequency when at max load since this is the opimum point.

  • It could also be your regulation.

    I used STW25NM500 MOSFETs.

    If you miss your leakage inductance your must insert a Lr of the rest value.
    E.g.: Total resonance inductance required at operation point (f_sw = f_resonance) = 10uH.

    If your leakage is measure to be 4uH, then your should insert a Lr of 6uH to total get 10uH resonance inductance.

    I coupled my circuit as shown: 

    With split resonance capacitors.

    Gate driver:

  • Gate driver: 

  • Hi CWilson

    Thanks for your reply.

    There's some good leads I will try to follow.

    I use a gate drive transformer, but it should't make the big difference as long as it doesn't cross conduct. I'll try to increase the dt to 300nsec. and see what happens.

    But the Lr value is probably the key to this problem. I'll do some test with this value and at the same time measure the current, pulse by pulse in the upper fet.

     

     

    Br

     

    Finn

  • Does it work?

  • Hi CWilson

    Yes it works just fine now.

    I took out 830W yesterday without any problem,  instability or so.

    Burstmode is also working very well now. I change from transformer gate driving to FAN7390 high/low side driver, which seems to work better in burstmode.

    So everything is "cool" right now.

    Thanks for your feedback to my problem which was very usefull.

    Br

    Finn

     

     

     

  • You're welcome :-)

    What is your efficiency?

    By measuring the voltage in the half bridge node (between the two MOSFETs) and measuring the two gate at the same time, so can see if your Lm is OK and that you're in ZVS all the time --> Your deadtime must be larger than the time it takes to V_halfbridge to go to zero.

    Press "Verified Answer" if everything is ok now.

  • Btw. I used a gate driver transformer and couldn't make the LLC work. Switched to IR2110 and everything was fine :-D

  • Eff. is around 95% which is ok for lab model. I haven't selected diode and fets for Fvd and Rds_on.

    My Ln ratio (Lm/Lr) 4.2 might be to low, but I'll check the ZVS/ZCS. I still have the 350nsec deadtime to reduce if there is a margin.

    Br

     

    Finn

  • Very nice efficiency since your ratio is low. I assume you're regulating on your output voltage via an opto coupler?

    I had a ratio of about 90 because it wasn't regulating. As I recall from the TI seminar 2010/2011, they recommend around 8-9 is you're regulating.

  • Hi CW

    Yes i'm in regulation with an output between 20V and 150V and current 0 - 10 Amps (limited by the max power).

    Output is acually very well regulated only few mV change with load changes. In burst-mode the voltage increase a few 100 mV which is Ok for this application.

    Regarding deadtime it is a trade-off between light loads and heavy loads so I thing i will stay in the mid zone.

    Eff. is poor in the low voltage end because of the Fwd o.m.a. I consider to try and SR solution.

    Br

    Finn

     

  • Super.

    I'm glad I could help.

    Yes Sync Rectification on the secondady side would help a lot at high current loads.

  • Please, with due regards to Mr. FINN, refer to my design and assist me further for prototyping hi-efficiency 500W 650VA LLC HALF BRIDGE STEP-UP DC-DC CONVERTER with fsw 60kHz.

    Design param

    Vin_min: 10,5V

    Vo_max: 375V

    Io-max: 1,35A

    1. Can I use MOSFET for primary side with anti-parallel zener diode (body diode)?
    2. I will be using EER3542 ferrite core transformer, so what do you suggest about Lm and Lr?
    3. Do you consider 1:50:50 turns ratio suitable?

    Pl, assist me to complete my design.

     

    http://www.wupload.com/file/2659584856/UCC25600.jpg

     

  • I've been reading these threads for a while - great info out there!

    I was wondering if anyone knows what the difference is between "Maximum Output Power (Pout)" vs "Maximum Power Limit (Plimit)" as defined in the Design Tool calculator?

    Thanks

  • Hello Mr Wilson,

    I'm new arround this community and PS designing also.

    Can you detail a little bit more your design (schematic, transformer core type, output voltage.....)?

    I've downloaded the spreadsheet and my Cs, Rs, Rp, Cp values are not valid (name??).

    My input data is

     

    Vin Min  290.0
    Vin Max 380.0

    Fsw  130.0

      Fswmax 350.0
    Fswmin   85.0
    P Lim 730.0
    P Out 700.0

    n     0.9

    Vout   60.0

    Thank you!

    Regards,

    George.

     

  • In fact both are the limits !

    I've not mastered UCC25600 yet however I would share my thoughts with you considering I may be of some help to you.

    The max power output is what you allow for peak loads whereas max power limit will be similar to burn-out condition to your circuitry.

  • Hi Kevin

    Maximum Power Limit (Plimit) determines the values of the detector to OC. When OC reaches a value of 1V (0.9 - 1.1) the gate outputs are low.

     

    Br

     

    Finn

     

  • Hi George,

    I don't have a schematic here, but I used the split resonance capacitor. See schematic here: http://e2e.ti.com/resized-image.ashx/__size/550x0/__key/CommunityServer-Discussions-Components-Files/188/4314.Unavngivet2.png 

    I used:
    Transformer: ETD39 3C90
    Freq: 100kHz

    Vin = 400VDC (from PFC).
    Vout = +/- 82VDC.

    Peak efficiency was around 97%. 

  • Great info also: http://www.google.dk/url?sa=t&rct=j&q=llc%20resonant%20huang%20hong&source=web&cd=3&ved=0CEIQFjAC&url=http%3A%2F%2Fdownload.21dianyuan.com%2Fdownload.php%3Fid%3D64104&ei=x0xCT_GACcrYsgaUw8ScDw&usg=AFQjCNF1Va4-9r5Vqxo6JbLpdBN1OLrj4A

    :-D It's almost a complete walk-through of the LLC.

  • George, I had the same problem.  You need to install the Analysis TookPak in Excel, then it will work properly.  The problem is that the first value uses some spreadsheet functions that are only installed with the Analysis ToolPak.

  • Great info... Thanks!

    CWilson said:

    Great info also: http://www.google.dk/url?sa=t&rct=j&q=llc%20resonant%20huang%20hong&source=web&cd=3&ved=0CEIQFjAC&url=http%3A%2F%2Fdownload.21dianyuan.com%2Fdownload.php%3Fid%3D64104&ei=x0xCT_GACcrYsgaUw8ScDw&usg=AFQjCNF1Va4-9r5Vqxo6JbLpdBN1OLrj4A

    :-D It's almost a complete walk-through of the LLC.

  • I hope you all get to know the LLC a little bit better. it's a tricky SMPS, but once you get to know it, you gotta love it.

    Read the papers (see the links) and understand the theory and then everything will be fine.

    Good luck. 

    Note:
    For unregulated converters the Lm/Lr ratio can be as high as around 80-90.
    For regulated convertes, it's recommended to design it to be around 9. See link from Hong Huang (my last link). 

  • I'm designing on off-line SMPS with a voltage doubler which yields Vin ranging from 240-375VDC.  I'm trying to get away with not using a PFC boost stage.  With such a large input range, do you still think Lm/Lr should be as high as 9?  When I do this, my fp drops to 56.6KHz, which I think would be too low.  Thanks for your thoughts.  Also, from the App notes, it seems like most designers try to stay below 150KHz to make EMI testing easier, but do you think there are advantages to running the switching freq. up to say 200Khz - since higher frequency should decrease the size of components (transformer, Output Caps, etc.) and maybe bring overall cost down?  Or maybe the higher frequency would create too much noise so that the additional EMI filtering would negate any space/cost savings in the higher freq.?  Plus, if kept in ZVS, there shouldn't be any EMI spikes as currents are sinusoidal, correct?  Thanks.

    CWilson said:

    I hope you all get to know the LLC a little bit better. it's a tricky SMPS, but once you get to know it, you gotta love it.

    Read the papers (see the links) and understand the theory and then everything will be fine.

    Good luck. 

    Note:
    For unregulated converters the Lm/Lr ratio can be as high as around 80-90.
    For regulated convertes, it's recommended to design it to be around 9. See link from Hong Huang (my last link). 

  • Hello Kevin,

    I'll try that after I'll finish reading all the docs that  CWilson gave us.

    Thank you!

    Regards,

    George.

     

  • Your ratio can be smaller.

    Follow the Hong Huang paper/guide to the regulated LLC and it should be fine :-)

  • Hello again Mr. Wilson,

    I've done all the calculations for my design, except the current sensing network. In the Rs calculus equation (UCC25600 datasheet), can you tell me what Prs is?

    Otherwise here are the other parameter:

    Vinmax=350V

    Vinmin=300V

    Vout=110V

    Iout=7A

    n=1,5

    Fs=122Khz

    Mgmin=1.03

    Mgmax=1.15

    Lr=25uH

    Cr=68nF

    Lm=100uH

    These are obtained using Hong Huang's document.

    Thank You in advance!

    George.

  • Your results seems resonable.

    I assume the P_RS is the power dissipation in the sense resistor. If you use 2512 resistors (500mW max each!), you can use 2 in parallel to even out the power loss in the sense resistors,

     

    I'm looking forward to hear from you regarding your results.

  • I also thought so, but obviously I was not sure. I realised that after I took a look on the equation and ohms= U*U/U*I=U/I

    Can you give your values so I can compare to mine?

    Thank you!

    Regards,

    George.

  • Mine was running without current limiter. It was a prototype to ensure the design and measure the efficiency.

    Use 2512 resistors and dont dissipate more than 500mW/each.

  • When I look through the LLC configuraion, I found the two kind of configuration, such as bridge rectifying and center-tap. What is the big difference between brige rectifying configuration and center-tap configuration at the secondary of transfomer? Is that from capacity?

  • You can config the LLC output to be plus and GND or plus, GND, minus.

  • Hi CW

    Having a so called "load dump" problem with another resonant converter.

    When going from a high load to no load, the stored energy damage the semiconducters.

    I do not know if you have solved this problem or never come into it?

    Is this done by clamping the half bridge fet's (paralleling the body diodes) or do I need some VBrds protection.

    Hope your still looking in here from time to time.

     

    Br

    Finn

     

     

  • It's great to use the ucc25600 resonant IC for the half-bridge DC-DC convert application  

     

  • Hi Finn,

    No sorry, havn't loaded the LLC with step-load responses so I haven't experiences the problems you described.

    Perhaps a TVS or similar from drain on high side mosfet to GND could solve it..?

    /Casper.

  • Hi CWilson,

    i searched info on google about llc and i found ur post.
    can you explain me for wich reason the LLC do not work with GDT?
    I plan to make a LLC unregulated smps with ucc25600 and GDT.
    Thank u
  • CWilson,

    Please start a new thread with your question, as this is an old thread from 2.5yrs ago. I am not certain about what is meant by GDT (gas discharge tube? other?). Please specify in your new thread to help our team help you.

    This thread is now closed.


    - Daniel

  • Hi,

    This Thesis is good to understand about LLC
    theses.lib.vt.edu/.../Wan_HM_T_2012.pdf