UCC28630EVM Test Problem

I assume that all of the data and waveforms were taken from the UCC28630 EVM572?

1. I don't quite see the "problem" here. Why are there 2 sets of numbers for both 115 V & 230 V, can you explain?

For sure there is a trade-off between the no-load regulation level and the standby power. If more output "pre-load" is added, to increase the standby power, then the no-load regulation performance will get better.

2. R18 is a very important resistor - this sets the "pre-load" power on the output, and is used to light the LED indicator. For PSR, the output can only be measured when there is a PWM cycle. So the controller must operate at or above a minimum value - for UCC28630 this is 200 Hz. The output pre-load has to be able to absorb a minimum amount of power equivalent to 0.5*Lpri*Ipk_min^2*Fsw_min. For the EVM, ths is 0.5*260uH*(0.172V/0.2ohm)^2*200Hz = 19.2 mW. In order to keep some margin above Fsw_min (if the controller hits Fsw_min, then the regulation will be lost), we recommend setting about 40 mW pre-load power for this example, so this is why R18 ~ 8.2 k-ohm. If R18 is removed or is increased in resistance too much, the egulation will be lost at no load, as was seen. Similarly, if R18 value is decreased, to take more pre-load power, then the no-load regulation will improve.

3. On/Off test - I need to know more details. What is the AC input and output power? What is the on/off cycle rate or on-time and off-time duration? What is the shutdown phenomenon? Does the EVM stay latched off and never come back on? Because this should not be possible. You have to be aware that the startup delay time is about 0.9 s typical at 90 Vac  for the EVM (see eqn 1 in datasheet). The startup time will be faster at higher AC input. So if the AC on/off time is too fast, the output will not start. Also depending on output load, once the IC recocgnises that AC input has dropped below UV level of 65 Vac, there is a 0.5 s delay before the Vdd pin is discharged, and the then the startup delay repeats. This is to ensure that the internal HV current sorce is not over-stressed thermally. So because of the start-up and shutdown delays, there is minimum repetition rate for on/off cycling. If the rate is to ofast, it will look like the power supply is not starting at all. This can be confirmed by checking the VDD rail during on/off cycling.

4. Because of the low Fsw_min (to try to get low standby power), transient response from no-load will always be poor with PSR. This is because the load step can happen just after a PWM cycle, and the controller will not be aware of the load step until the next cycle, possibly up to 5 ms later. So the output drrop depends on the output cap and load current. For the EVM, the worst case drop can be as bad as 12 V! (dv = (di/C)*dt).

If the output pre-load or min load is increased, this will force higher switching freq, which will improve transient response.

For load steps where Imin > ~100 mA, the transient reponse should be ok. in the plot you show for 50%-75% transients, the output deviation is about +/-250 mV - that's about +/-1.25%, I thinks that's actually not so bad. The deviation can be improved slightly by adding more output cap, but the improvement is small.

5. The constant-resistance mode is only required in order to test the CC mode. This is always the case with any PSU that supports CC mode output. Because the PSU output CC characteristic is connected to an E-load with an input CC characteristic, then the two systems will "fight" at the CC point, where the PSU wants to regulate at say 6.0 A, but the CC load may want to take a constant 6.1 A - in this case, the PSU output will collapse, shitdown and restart. For CC output testing, a CR load must always be used, so as the load resistance drops, the PSU will deliver regulated CC curent into the resistance, and the resulting output voltage will drop linearly as Rload drops.

I hope this answers the questions.

Thanks,

Bernard