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-/+400v push pull design not responding to transient load

Other Parts Discussed in Thread: UC3825

hi

I have design a push-pull 22v to -/+400v supply @20mA each and is stable but when I load the circuit with op amps producing a 0-250v raster at 1Khz then I get a ripple of 1% on my 400v. I require a ripple of 0.25v. the design is in voltage mode, as there is not a large load. Also my sense resistor gets hot, but not my transformer.  So I don't think its going into saturation. The CT RT is set at 90Khz for the pwm

part is a UC3825.

Any one got any ideas? I have tried type 2 compensation without success.

 

  • Hello Ross,

    I have an idea of what the problem may be. FIrst is there ripple on the 22 V input?  Also, have you measured the voltage across the sense resistor? You can tell from this voltage whether or not you are saturating. See the figure below:

    Be advised that the drawings of the voltage waveforms are ideal and you may see gradual changes in slope and the saturated waveforms may skip over some normal waveforms. This is because the current may be "walking" up the BH curve of the primary inductance. I suspect that the saturation is very gradual and you may be hitting saturation at the frequency of your output ripple. 

    Voltage mode push pull converters are notorious for having saturation problems. This is due to imbalances created by different RDS on values in the MOSFETS and slightly different on times. Normally in a buck-derived topology, the transformer DC bias point is zero. In the push-pull converter, there are two unmatched, alternating, primary side switches so the volt-seconds on is either greater than or less than the volt-seconds off in the transformer primary and a DC bias point is created in the push pull transformer BH curve.  Over time this bias point "walks" up the BH curve until it hits saturation. 

    If you have ripple on your input voltage, and by some miracle you are not in saturation, the problem could be the fact that you have selected voltage mode as a control method. Voltage mode control has poor line or input ripple rejection. This is due to the feedback voltage having to travel through output filter - in a push pull, this is the secondary side inductance and the output capacitor- and back to the input. 

    If you have a small saturation problem and it is causing the output voltage ripple, you either need a transformer with a bigger core or more turns on its primary. Or you need to change the topology of your DC DC to maybe a forward or even a fllyback. I would either choose current mode control or augment the voltage mode control with a feed forward network to reject line ripple.

    Hope this helps,

    Chuck

  • hi Chuck

    thanks for the suggestion, i have checked the waveform and I don't see it change in the slope as suggested. I did think it might have been saturation, but hopefully this has eliminated it.  I can change my raster to 10hertz and the ripple follows this, 4v pk/pk

    Also then not restering the 400v is stable, the ripple is 200mv, if it was going into saturation then this would be also unstable. I do see a loading on the supply that i will look into, but this is at a higher frequency than the raster, intime with the gate voltage to the fets, looks like some shoot through. This might be why my current sense resistor is hot.

    I think I need to relook at my feedback?

    cheers

    Ross

  • Hi Ross,

    Ok, so you're not saturating probably because the load power is very small.

    "Also then not restering the 400v is stable, the ripple is 200mv, if it was going into saturation then this would be also unstable."

    When the you are not rastering, don't you draw low current? Then if you draw low current you also may not be saturating. So I'm not sure that stable operation at light load is proof you are not saturating.

    If you have a shoot through condition you should be able to see that in the primary side current sense resistor voltage waveform. I don't have the schematic to check this, so I am assuming the current sense resistor is on the primary side in series with the MOSFET source to ground. If so you would see a wave-form similar to the saturation condition wave-form. 

    Shoot though can be caused by not enough deadtime between the time when one MOSFET turns on and the alternating MOSFET turn off, or Cdv/dt false turn. C dv/dt false turn on occurs when one MOSFET turns off and creates a high dv/dt voltage at the switching node where the two drains of the MOSFETs connect. The following explanation is from the TI apnote slup206 by Brian Lynch and Kurt Hesse. The appnote is about the sync buck, but this phenomena applies to all half-bridge, or buck derived topologies where there is a switching node shared by two MOSFETs. The only difference between the sync buck and the push pull is the switches are tied parallel instead of series. 

    "When the SW node starts to rise, the drain voltage of the SR MOSFET (Or in you case the altenate MOSFET) rises as well. The rate of rise causes currents to flow in the parasitic MOSFET capacitors. Current through Cdg must go into either Cgs or be shunted through the gate lead and returned to GND by the driver. Current not shunted around the MOSFET causes the voltage on Cgs to rise. If this voltage rises to the threshold voltage of the MOSFET, the rectifier MOSFET turns on and shoot through current flows. The oscilloscope waveform in the figure below shows an SR gate “spike” during the rising edge of the SW node." The grey line is current, the small bump is the shoot through. This figure actually shows an acceptable current bump. Some small dv/dt turn on is expected.

    This is Lynch and Hesse's solution:

    "The best line of defense to parasitic turn ON is to keep the impedance from the gate to source of the SR as low as possible. Close attention should be paid to the layout of the gate drive circuit. The circuit should be low resistance, (a wide, short track) and low inductance (a wide track with a GND return path directly beneath it) Minimize the loop area in the circuit and use a ground plane effectively. Also, use a driver or control IC that has a very low pull down (or sinking) impedance. Also, reducing the rate of rise of the SW node with either a snubber or by limiting gate drive to the main switch can help to minimize the problem."

    I would add that you need to check the Cgd and Cgs ratio of your MOSFET and make sure they don't form voltage divider high enough to turn on the MOSFET. 

    Addressing the problem of the voltage feedback loop, I would solve the issue of the hot sense resistor first. This is because the ripple follows the raster frequency. During high load conditions you get the high ripple voltages, so it appears to me the two are related. 

    What is the bandwidth of the voltage mode loop gain? Voltage mode has poor ripple rejection but does have some and you should be able to handle 10 to 400 Hz ripple,unless they are very high due to the shoot through phenomena. If you fix the hot sense resistor and are sure you don't have problems with either saturation or shoot though, then you should look at the voltage mode feedback. Then I think you either need to add a feedforward network or change to current mode.

    Chuck

     

  • Hi Chuck

    i have done some more testing and changed my feedback to a type 2 compensation, as i had it wrong. now the ripple is gone under load of -3-4ma raster and 200mv ripple at 5ma which is fine but i have the problem of either the transformer heating up or the rsense gets too hot, or both. I have noticed that on the fet drains then is little ringing and the signal is switch on 40v then a decay to about 2v before the other transform switches on, this seem wrong but don't know why, the mark on is 0.5us and the switching is 80khz. if i increase the switch 80k the rsense get hot. can you help please?

    i expected some ringing even with my snubbers

    regards

    Ross

  • Hi Ross,

    Congratulations on fixing the ripple voltage problem.

    If you are using voltage mode with a type II compensator, then you need to be using electrolytic output capacitors with moderate esr so that you get enough boost from the zero formed by the output capacitance and the capacitor esr. probably 50 to 100 m ohms at least. If you are using ceramics as output capacitors I would use a type III compensator. I think this would be best since you need a good transient response.

    The key to finding the problem is carefully examining the current sense voltage waveforms and the MOSFET drain-to-source waveforms. You indicate in your email that you are observing a little ringing on the drain to source node of the MOSFETs. How do you define a little ringing? Is it 1%, 10% of the input voltage or 50%?

    If these waveforms are correct then the over heating has to be due to the under sizing of the components. Since I don't know the details of your design I can't be sure what the problem is. However I can give some general suggestions. For one, the easiest way to check the current sense resistor over-heating problem is to verify that the current passing through it is not too large. The waveform shoud be like the one I showed you in the previous email. Check the rms value of the current passing through it and make sure the power rating of the sense resistor is adequate. Also how do you define hot? Is it hotter than the specified maximum temperature of the resistor? Also, if the sense resistor has been stressed to a higher temperature than what it was designed for, the value of the sense resistor has probably increased. 

    As to the transformer, if you are satisfied that the transformer is not saturating, then you need to be sure the windings are sized correctly for the power you are passing through it. You need to look at the winding skin effect and proximity losses. The output voltage of you converter is quite high compared to the input voltage. You probably high very high reverse recovery losses in the output rectifier. I would check the Qrr of these diodes. Maybe you can use SiC diodes.

    Can you send me the MOSFET drain to source, gate to source, and current sense resistor waveforms? I could probably be of more help if I knew more about your design.

    Chuck

  • hI Chuck

    here are the wave forms gate to source, tr11 source is connected to the transformer.  

    gate rsense and rsence, rsense is on the drain TR11.

      

    as you can see the ringing is small. the output is a 22mH output capacitor is a ceramic 10pf. 

    The temp of the rsence and the transformer is about 50c constant. i think this is a bit high as rsence is a 7 watt 0.22r resistor. It is still a type 2 system.

    regards

    Ross

  • You can fix this my adding an RC snubber across the output rectifier diodes. Or you can choose output rectifier diodes with lower Qrr, like ultrafast or SiC. 

    A 50 deg C rise in temp is acceptable for a transformer design and the resistor as well. 

    If these waveforms are at maximum load, the duty cycle is very small -20%. Is this to prevent the transformer saturation or cross conduction? I would probably adjust the transformer turns ratio so that you get at least 40% duty cycle at maximum load. The inductor value of 22 mH is good by my calculations, for a 40% duty cycle, 30% delta Il, and 20% deadtime. I get 22pF for output capacitor.

    Have you checked your phase margin and gain margin with the type 2 to be sure you are stable? Most designer's I know and work with recommend a type 3 controller when using a ceramic output cap and voltage mode control. Refer to the TI apnote slup233. They state in this app that the reason you need to use a type 3 controller is that you lose a phase boost formed by the esr of the output cap and the cap. If you use a ceramic cap, the esr is very low and the zero, or phase boost is pushed out to very high frequency causing the loop to become marginally stable. This could be what is causing the ripple at currents above 5 ma. 

    Chuck

  • hi chuck

    thankyou for the information. I am using a US1M diode in the bridge 75ns response, ultra fast, so fining a faster one above 800v is hard to find. I dont have room to fit a snubber in the circuit.

    quick question how did you come to the 22pF output capacitor as that would put the freq FLC about 228khz.

    I am still looking at this as i have a noise on a 375v rastering signal, which may be the response is too slow. I will look at puting a type 3 on.

    regards

    Ross

  • Hi Ross,

    My output capacitor calculation was way off. So you should probably ignore it. I don't have any experience with rastering. I don't know what FLC means. I assume it has something to do with flickering. I only know about low to high voltage push-pull converters. I have designed thirty or more in my career. Mostly for HFPA rails or audio amp rails. If there is something special going on at the output of  your converter since it is a video application, then my two cents isn't worth much.

    You can get a 1200V SiC diode, C4D02120E, that has 150uA reverse recovery current. It's a Dpak instead of an SMA and about 5 times the cost so you probably wouldn't need it. 

    The output capacitor value I calculated was way off. I recalculated it and got a value of 56 nF. That's with the following assumptions:

    The maximum output current is 22mA

    The delta inductor current is 30% of the output current, or 6.6mA

    The maximum ripple voltage on the output is 0.5% of Vo or 200 mV

    That results in an output inductor of 145 mH and an output capacitor of 51.5nF or scv or 56nF.

     

    I guess there is more going on at the converter output than a resistive load, so maybe these values are useless.

    I have attached a file on my local email with the calculations. I hope this helps.

    Chuck

  • hi Chuck

    thankyou for all the help. The FLC is the frequency for the output LC circuit which gives the poles. The max current is 5-6mA. The design is controlling a deflection plates for a x-ray beam. I am having difficulty in specifying the output capacitor ESR so assumed about 3mohms, as the is a ceramic, 10nF 1000V though hole cap. datasheet does not say so, is this a good guess?

    Please could you send me you calculations, as i might have this wrong. I still need to check my phase margin and gain margin. My feedback is a type 2 now, with a rc (91k 47nf) parallel with c 1nF. 10k input r. 

    The transformer is calculated as a 3-64 turns ratio with a 22v input for a 400v output, so the mark would be small. is there any benefit to increasing the turns ratio for a larger mark?

    regards

    Ross

  • Ross,

    I know what the problem is with your converter, if the following is true:

    The output inductor value is 22 mH

    The output capacitor is 10 nF

    The maximum load is 6 mA

    The turns ratio is 3 to 63

    The problem is you have set the inductor value so low that you are running your converter in what is known as "discontinuous" mode. This means that the peak to peak value of the current running through your output inductor is greater than you load current. In fact it's 22 ma, by my calculations. When this happens, the output of your converter is no longer a function of the duty cycle, it becomes a variable function of the load.

    All of the Type I, Type II, Type III compensation loops assume that the converter is in "continous" conduction mode.

    To keep the converter in continuous mode, you need to increase the value of your input inductor so that the peak to peak current through it about 2 ma, or 30% of the load current. I calculate this to be about 270 mH. To get 0.25% output voltage ripple with a ceramic cap, you need a value of 16 nH.

    Don't worry that the FLC, or corner frequency of the LC filter is less than 10 KHz. I calculate it to be about 2.5 KHz. This is fine. When you add gain to the loop using the error amp you can increase your bandwidth to whatever you need practically. 

    The 3 to 63 turns ratio on the transformer is fine. 

    I will provide you the details of my calculations later tomorrow.

  • Hi

    thanks, i assume that the above is 270mH and 16nF cap. a typo above

    270mh is large. I can get 47mH in the same package, but the corner freq would increase to 7.2k with a 10nF cap. Or i can get a 100mH and fit it in. I know the ripple will increase but is 100mH large enough?

    regards Ross

  • ross,

    Yes, that was a typo, 16 nF is right.

    I want to make sure your understand that the corner frequency of your LC filter does not limit the small signal frequency response of your filter.

    If you increase your converter's switching frequency to 166 KHz and allow 40% ripple you can use a 100 mH inductor and stay in continuous conduction mode. You need a 10 nF capacitor to stay under 0.5% ripple at full load. You will need to redesign the transformer to accommodate higher losses due to higher proximity effects. The core size should go down considerably leaving you more room. I would use multiple, low diameter strands of magnet wire on the primary. The diode reverse recovery current should decrease because of the shortened on and off times. So the sense resistor should not get any hotter. 

    Hope this helps,

    Chuck

  • Hi Chuck

    i have done the calculations for redesign of the transformer. My core is rm10/I-3c90 with an ae of 0.966mm. If my input is 22v and output is 400v (470v max no loss). keeping flux BE below 1200 and a switching freq of 160K. If i choose 40% and account for losses i get a 12 turns primary (NP) and 256 turns NS. I can not fit that onto the bobbin. note its a dual output -400 and +400v.

    I have 3 np and 64 ns, which is 10% assuming 470v max no loss transformer. if i increase my frequency to 160k I can keep the transformer as is is this correct or am missing something. as my flux BE is still ok.

    Plus can you send me the calcs cheers

    Ross

  • Hi Chuck

    I have been investigating my systems power and found that running the raster under certain operations takes 10- 11mA. This causes some ripple and noise that my power amps amplify to a cause the raster to get noise on it. which is undesirable.

    with no raster and no opamp my power is about 4ma

    with a fix voltage offset and certain rasters its about 6ma. 

    because of the different operations with different electron beams the rasters are produced from different opamp circuits with i did not realize the power taken. my power is +400 1.6w to 4w and -400v 1.6w to 4watts

    you mentioned previously that my 6ma max was  really 22ma can you explain.

    cheers

    Ross

     

  • Hi ross,

    The 22 mA value is for the peak-to-peak current that flows through the output inductor. If you have a switching frequency of 80 KHz, a load current of 6 ma, and an output inductor of 22 mH, your peak-to-peak inductor current is 22 ma. Since the peak-to-peak inductor current is larger than 1/2 your load current, the inductor current less than 6 ma is cut-off by the output rectifiers and your converter drops into what is known as "discontinous" mode. The push-pull converters are not usually run in discontinuous mode since the duty cycle becomes "load dependent". The small-signal model must be re-derived and the usual methods of network compensation do not apply. 

    That is why I suggested you increase your switching frequency and output inductor value. 

    Google the following

    LM5030 Mathcad Design Tools

    Don't worry if you don't have access to Mathcad.  There is a pdf and word file that describes the push-pull equations.

    Good luck,

    Chuck

    and you will find all the equations needed to design a push-pull converter. 

  • Hi Chuck

    thanks for the data, i have been working through the calculations and for a 22v input nom, 400v output at 0.01a max, 4ma min, with a 0.25v ripple. 160k switching freq with a diode drop of 1.7v,  FET rds 0.044v, i get 0.08H inductor using 100mH and 500nF cap, 

    transformer eff 75% duty cycle 0.365

    does this seem correct?

    cheers

    Ross