LM25037 delay time and soft start

If you look at the IC block diagram on page 8 of the LM25037 datasheet, you can see that there is no dependency between the FB pin and the SS pin.

If the FB pin is connected to GND, this will force the error output (at the COMP pin) to go high, through the 5 k internal pull-up to the internal 5 V rail, as shown.

The SS pin is internally shorted to GND by the "Shutdown" internal signal until all internal IC power good conditions are ok (VCC ok, VREF ok, etc). The SS pin voltage is connected to the "SS Buffer", shown below the COMP pin. This buffer will independently pull down the COMP pin to force the COMP pin to track the SS pin, until the SS pin increases above the COMP level, then the COMP level is controller only by the error amp. This is because the SS Buffer open-drain output can only pull-down the COMP, it can cannot pull it up.

So after the "Shutdown" signal goes low (when all internal rails are good), the SS pin external cap is charged through 100 uA current source. The dv/dt on the SS is matched at the COMP pin by the "SS Buffer" circuit. When COMP level exceeds the 1 V offset, then the PWM starts, with narrow pulse width, and the pulse width increases as COMP & SS rise together.

Since the COMP & SS pins have to charge from zero to the ~1 V internal offset before the PWM starts, this causes a delay. This delay will depend on the value of the SS cap, and can be calculated from the cap value, and the value of the internal 100 uA charging current source. Nominal delay is 10 us for every 1 nF of capacitance on the SS pin.