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UCC28950 Current Imbalance: 1200W Interleaved Phase Shifted Bridge

Matthew Mikalauskas
Prodigy 130 points
Other Parts Discussed in Thread: PMP6712

I recently completed a design which has an architecture similar to the TI reference design "PMP6712_REVD_: 1600W Isolated Power Interleaved Phase Shifted Bridge".  The specifications are:

1200W variable output supply, +92% efficiency
Vin = 22 to 30V
Vout = 16v to 25v

For a constant load power, for higher input voltages (> 27v) the stages are balanced with ~ 8%, however, once the input
voltages start descending below 26v the current imbalance between each stage gets larger with imbalances exceeding 19%. The
imbalance always favors the Slave stage which contributes more power to the load than the Master. The only exception I will soon
describe in the 1200W section below.

Waveform Plots:
- measurements across secondary transformer shunt resistors
- YEL = Master (across R6//R7 in reference design), BLU = SLAVE (across R54//R55 in reference design)

800W Load, Vout ~ 20.4v
----------------------------
800W Waveforms: minimal current imbalance @ 28VDC that slightly increases with decreasing input voltage (25VDC & 24VDC)


1200W Load, Vout ~ 24.9v
----------------------------
"1200W @ 28VDC IN" waveform: discernible current imbalance @ 28VDC
"1200W @ 25VDC IN" waveform: significant current imbalance @ 25VDC
"1200W @ 24VDC IN" waveform: current imbalance reversal - Master Stage providing bulk of the load power with Slave stage greatly reduced

In our normal application this will not be an issue, however, I just now witnessed this phenomenon and would like to understand the root cause
of these current imbalances. I will start my investigation on Monday, however, if anyone could shed any light on this issue it will be greatly appreciated

Thanks,

Matt

Test Cases 1-30-15.docx2783.Test Cases 1-30-15.docx435slura08.pdf

 

 

  • 0
    Prodigy 50 points
    Matt,
    I suspect that you have solved your problem by now and if so, would like to hear what you discovered.
    If you still have the problem, here is what I notice. The mechanism for making the currents equal is current mode control where the current sense is compared to the comp voltage to determine pulse width. However, to fix an inherent instability with pulse widths over 50%, artificial slope is added. With a lot of slope compensation added, it becomes more of a voltage mode control than current mode and in my opinion loses the current sharing control.
  • 0 in reply to Jim Walker61
    TI__Mastermind 25570 points
    Hello Matt
    This is what I think - (guess)

    Jim's point about slope compensation is valid - it would be worthwhile checking the amount of slope compensation you are applying - the value of the resistor at RSUM.

    Given that the imbalance is always in the same direction (slave supplies more than master) then I would suspect some systematic differences in the power circuit rather than in the controller. You could check this by swapping the controllers over and seeing whether the imbalance follows the controller or remains the same.
    By systematic difference I mean that the two power circuits are not actually symmetrical. I would think of things like:
    A/ Are the Current sensing circuits the same - I'm thinking of layout issues here - for example, are the current transformers oriented in the same direction relative to other magnetic fields that may impinge on them - eg field from the power transformers.
    B/ Is there some systematic difference in the slope compensation ? The PCB layout at the RSUM pins should be symmetrical
    C/ Is the magnetizing inductance of the two transformers the same and are the layouts of the two power stages similar.
    The ramp that the controller uses to terminate the cycle is the sum of the CS signal, the slope compensation, the output current, the magnetizing current

    The current imbalance reversal may be due to the slave going into a current limit condition.

    I'd swap the controllers just to make sure the fault doesn't follow them then having done that I'd start looking for some systemic differences between the two power trains and their layouts.

    Regards
    Colin
  • 0 in reply to Colin Gillmor
    Prodigy 130 points

    Hi Colin/Jim,

    Thanks for the feedback. I was able to run the slave stage (master disabled) in open-loop to help identify any uniqueness that was not observable with the master stage running independently. This helped me identify some noise sources that were corrupting my current feedback and master compensation feedback to this slave stage.

    Both PWM controllers are separate SMD adapter cards that are soldered to the main SMPS PCB. The slave stage adapter card had some via's that coupled/interacted with the some of the main SMPS PCB vias and traces which corrupting these feedback paths. I isolated each of the PWM controller adapter cards with 0.006" insulating film that resolved the current imbalance and some other subtle issues that I had.

    I also was able to resolve an intermittent ignition phenomenon by adjusting the slope compensation. By lowering the slope compensation by 40%, I am now able to have consistent ignition throughout the input voltage and output power ranges (22VDC-32VDC and 400W to 1400W, respectively, with a variable output voltage between 15VDC and 27VDC).

    Other than that, it appears everything is running spectacularly! I attached some quick waveform plots that depict the current balancing of both the master and slave stages over a range of input voltages and load power levels. Note: I had a relatively poor ground on the VIO (Slave) channel.Primary Current Waveforms, Balanced.docx

    Thanks again for your advise and feedback,

    Matt

     

  • 0 in reply to Matthew Mikalauskas
    TI__Mastermind 25570 points
    Hi Matt
    It's good to hear that you were able to solve the problem and thank you for the summary.
    Regards
    Colin