I'm working on a consumer product which looks like a perfect fit for a UCC38086. Summing a sloping compensation current to the current signal filter looks like an excellent idea. I'm eager to try it but I'm having trouble understanding some of the details in the datasheet:
The Current Sense filter cap, CF in fig 1 is 220uF, application schematic (page 8) is 220pF, figure 7 is 220kOhms. A value of 220pF makes sense. Is it 220pF?
Figure 1 labels the signal from the current sense resistor (RS) connected to the top of RF as “VCS”. This looks like it’s supposed to be VRS? If it is then figure 1 would match figure 3.
I can’t make out the meaning of the term “RAMP VOLTAGE HEIGHT”, which is in equation 2 on page 6. If I’m not mistaken this is the crux of understanding the part. Here where I’m getting confused:
Referring to the internal block diagram on page 5, the resistor connected from Iset to GND (pin2) forms a current sink, whose output is Vct/Rset. The block diagram labels the + input of the amp as “CT”, but that really should be Vct, which is the voltage developed across CT? More on this in a moment.
Vct should always range from 0.2V to 1.5V, shouldn’t it (neglecting temperature and delay effects)? Ct is charged by a current set by Rt and it’s discharged by the fet shown next to Ct? The window comparator for the osc uses 1.5V and 0.2V as limits. Is this correct?
Back to Islope: The current sink controlled by Rset is turned into a current source and multiplied by 5 to form Islope, therefore Iset = Vct/Rset and Islope = 5(Vct/Rset)? Let’s consider the quiescent case of 0 output current (Vrs=0) and Rset=50K. If Rset=50 then Islope would start at 20uA when Vct=0.2 and rise to a peak of 150uA @ Vct=1.5V? If the recommended value of Rf=1K is used, then the voltage at the CS pin would rise (after charging CF) from 20mV to 150mV? In this case would the value of equation 2 for “RAMP VOLTAGE HEIGHT” be 130mV or 150mV?
Let’s take the case of the output voltage at 0, and the current in the sense resistor causes Vrs to ramp from 0 to 150mV. The voltage at the CS pin (Vcs) would then ramp from 20mV to 300mV, using the compansating ramp of 150uA described above?
Referring to the “PWM Comparator/Latch” section on page 5, it appears that if the voltage at the CS pin exceeds 0.5V then the PWM latch would be triggered directly through an OR gate and the PWM comparator is not involved. This is the confusing part for me. The - (middle -) input to the PWM comparator must then be < 0.5V for the part to be useful? If the voltage at the CTRL pin exceeds 1.17V then the output of the PWM comparator would never trip the PWM latch?? I thought this part was designed to run when the CTRL pin is pulled low? How is that supposed to work if the middle - input to the PWM comparator is at 0V?? Wouldn’t the comparator always be high in that case, because of the 300mV offset summed internally to the + input of the PWM comparator?
I would sincerely appreciate your clarification.
Steve
Edit as of 7:18PM:
Correction to that last paragraph, the application schematic shows that the device will run when the CTRL pin is NOT held low, got that backwards. My basic question still remains, I'm still not clear about the gain of the PWM comparator section. The + input of the PWM is the terminal where is the ramp is present. When the + input is greater than the middle - terminal then the PWM latch is set. If the max input of the CS pin is 0.5V (when the latch is set anyway), then is the full swing at the + input (when duty cycle = 0) when the + input is at 0.8V? If so then the middle - input should not exceed 0.8? And the swing from 50% to 0% occur when the occurs when the middle - input of the PWM comparator (which is the slow moving voltage control input) moves from 300mV to 800mV?
Edit as of 7:53PM:
I just found SLUA584A which answered most of my questions regarding the current injection into the filter on the CS pin. I'm still not clear about the voltage input , specifically the recommended values of the pullup resistor between CTRL and VDD, and how that value is computed. Should this value be chosen so that - input of the PWM comparator is at in the middle of the range, for example 0.5V? Figure 1 in the datasheets suggests a value of 10K, but no voltage is given for the VDD pin. A 10K value would set a resistor divider ratio of 0.4 from the CTRL pin to the - input of the PWM comparator. When VDD=5V that would mean 2V on the - input of the PWM comparator. That doesn't seem right. Is a divider ratio closer to 0.04 closer to the values presented? That would be a 1.36Mohm resistor?
