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UC1845 what is the minimum output non-zero pulse width?

In my application I must (at times) operate at low duty cycle, output is 500khz (1meg osc).  I must operate at 2% duty cycle, which requires 40ns output on-time.  The part outputs 0us on time with comp<0.5v, and jumps to about 140ns 0.5v<comp<0.9v.  It seems to be unable to make an output pulse width between 0us and 140ns.  Is this worst case minimum output pulse width defined anywhere with tolerance and temperature variation?  The data sheet specifies minimum as 0%, which does not answer my question.  The block diagram does not help understanding.   My Vcc is 16v and I'm using the -ep part.  Thank you,

Bill

  • Hi Bill,

    I think the issue is that there is a typical 150ns delay in the CS block which is time taken from when the CS voltage exceeds the COMP pin value to the output pin going low. See page 4 of the datasheet, Current sense section, last line.

    Regards

    Peter