The external synchronization pulse for LM25117Q

Hello Hackett-san,

I appreciate your prompt reply.

Please let me ask you additional three questions.

①I intend to input a signal of 5V to 0v into the RT pin through
   a buffer currently.
   Is there any issue?
     *Cf. attached file circuit.xlsx

7510.circuit.xlsx
②It is described to 7.3.3 in data sheets P15 that "This may limit
    the duty cycle of external synchronization pulse.
　 However,from your answer,I understand that the external synchronization
    pulse is not limited about the duty cycle.
    Is my understanding correct?

③Could you please show me the function block diagram including internal regulator
    around the RT pin?
    I would like to understand how the internal regulator and RT pin are connected
    for when I consider the other external circuit for the external synchronization pulse.

Best regards.

Hello Lee-san,

I appreciate your prompt reply.

I'm terribly sorry for mistaking your name.

I'd like to ask Lee-san additional three questions.

①I intend to input a signal of 5V to 0v into the RT pin through
    a buffer currently.
    Is there any issue?
      *Cf. attached file circuit.xlsx

       5340.circuit.xlsx
②It is described to 7.3.3 in data sheets P15 that "This may limit
    the duty cycle of external synchronization pulse.
　 However,from your answer,I understand that the external synchronization
    pulse is not limited about the duty cycle.
    Is my understanding correct?

③Could you please show me the function block diagram including internal regulator
    around the RT pin?
    I would like to understand how the internal regulator and RT pin are connected
    for when I consider the other external circuit for the external synchronization pulse.

Best regards.

Tsuyoshi Tokumoto

Hi Lee-san,

  Thank you for your prompt reply.

  Please let me ask you a question about A2).

  Q1)  Would you please tell me the calculation method of that limit?

Best regards.

Tsuyoshi Tokumoto

Hello Lee-san,

Thank you for your prompt reply.

I understand your answer.

Please let me ask you additional two questions.

I think a method of designing the values of RT and Csync as follows.
(The RT and Csync are connected to the RT pin)

①I set the values of RT and Csync to the value calculated based on the value
　 of C5(100pF) and R8(22.1kΩ) in data sheets P22 Figure29 at first.
　 The calculation formula is as follows.

         Csync×RT＝100p×22.1k

    ex）When the RT is 6.8kΩ,
　　　    　Csync=100×22.1/6.8=325pF

②Then I confirm the input waveforms of RT pin with the above values on the board,
　 and if necessary,I readjust the value of Csync.

Question 1) Is my way of thinking reasonable?

My customer designed the circuit which inputted the external synchronization pulse
into RT pin directly without the capacitor on the past.
*Cf. attached file past_circuit.xlsx

past_circuit.xlsx

However,the circuit seems to work correctly by the external synchronization pulse currently.

Question 2)Is there a possibility that any issue will occur from now on?

Best regards.
Tsuyoshi Tokumoto

Hello Lee-san,

　Thank you for your reply.

　I understand your answer.

　Could you reply about question 2?

Best regards.
Tsuyoshi Tokumoto

Hi 

It is not recommended to connect the external synchronization pulse directly to the RT pin.

This configuration has not been evaluated thoroughly. Without the AC coupling capacitor, the device has no chance to detect RT resistor value since RT pin never be in regulation.  

Regards,

EL

Hello Lee-san,

　I measured the RT pin voltage by using LM25117_EVM, when I inputted the external clock signal
to the RT pin through the C5 capacitor which I changed the value of.
In addition,I measured the RT pin voltage under the conditions of around Vin voltage 5V,
because the Vin voltage of my customer's design specification for LM25117 is 5V.
I attached the file of measurement circuit and result.

Evaluation of Ext CLK.xlsx

I have two questions about the measurement result.

Q1) From the measurement result,I will recommend my customer to use the C5 capacitor
       whose value will be between 470pF and 1000pF.
       If 1000pF is used to the C5 capacitance, is there any problem?

Q2) It seems to me that the internal SYNC circuit has voltage characteristics
       around the Vin voltage 5V.
       In addition,the RT pin voltage waveform is stable at the Vin voltage 6V or more.
       Does the internal SYNC circuit have voltage characteristics around the Vin voltage 5V actually?

Best regards.
Tsuyoshi Tokumoto

Hi Tokumoto-san 

A1)  The best way is to use 100pF with a small duty cycle synchronization pulse. If you cannot make the duty cycle small, please add a schottky diode at RT pin to prevent excessive under-voltage. 

A2) I think RT regulator strength is changed when Vin is low. 

Regards,

EL

Hello Lee-san,

Thank you very much for your prompt reply and your advice.

What kind of issue will occur,if the C5 capacitor value is increased?

We would like to use the 470pF capacitor if the value of 1000pF is
too large, because my customer cannot to change the duty cycle or
add the schottkey diode.

According to a past post, the 390pF capacitor is usable.

  e2e.ti.com/.../310420

I think that the 470pF capacitor may be usable.

Is the 470pF capacitor usable?

Best regards.
Tsuyoshi Tokumoto

Hello Lee-san,

Thank you very much for your prompt reply and your advice.

I understand your concern.
I will discuss the capacitance value,the duty cycle and the adding schottkey diode
with my customer, and I will re-evaluate it.

I would like you to tell me one point.

In the evaluation,if I increase the coupling capacitor value,
is there anything that I should confirm carefully?

Thank you for your cooperation.

Best regards.
Tsuyoshi Tokumoto

Hello Lee-san,

Thank you for your continued cooperation.

I have a question about the timing of inputting the external clock and an
Enable(UVLO pin) signal.
If the external clock and the Enable signal become active at the same time,
will there be any problem?
*Cf. attached file lm25117_extclk.xlsx

lm25117_extclk.xlsx

If you have the recommended timing,could you please tell me it?

Best regards.
Tsuyoshi Tokumoto

Hello Lee-san,

Thank you very much for your reply.

Please let me ask you additional question.

I think that when the UVLO pin is Low level,most of the internal
bias circuit in LM25117Q doesn't work.

When the high level signal is applied to the RT pin
under the conditions that the internal bias circuit doesn't work,
does some of the internal circuit not have unexpected behavior?

If you have some concern, could you please tell me the setup time
until the internal bias circuit works correctly after the rising edge
of Enable(UVLO) signal?

I'd like to suggest to my customer that the setup time is necessary
before starting up the external clock.

Best regards.
Tsuyoshi Tokumoto

Hi Tokumoto-san

Because VCC regulator turns on when UVLO>1.2V and there is no switching until VCC>VCC_UVLO, you don't worry about it.

Regards,

EL

Hi Lee-san,

Thank you very much for your reply.

I answered to my customer with your reply.

However,please let me ask you one more question.

I asked TI team same question regarding to TPS54618Q1,
and the advice from TI products team was as below.

"This should be safe, as long as VIN is high when the clock is applied.
Applying the clock before VIN is normal, because suddenly applying/removing
the clock during regulation will cause some overshoot/undershoot response,
which some customers prefer to avoid.
Applying the clock after EN, or during regulation , will cause some overshoot/undershoot
because of the part needs to transition from free-running to PLL mode."

Is the LM25117Q also same as TPS54618Q?

About applying the clock of LM25117Q, which one do you suggest
after rising of EN signal or before rising of EN signal?

I'd like some advice.

Best regards.
Tsuyoshi Tokumoto

Hi Lee-san,

 Could you please give me some kind of advice?
 I need to reply to my customer about that question.

Best regards.
Tsuyoshi Tokumoto

Hi Lee-san,

　Thank you very much for your kind reply.
　I would appreciate your cooperation.

Best regards.
Tsuyoshi Tokumoto