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UCC28700 stability

Other Parts Discussed in Thread: UCC28700, PMP10415, UCC28730

Hello,

I'm working on a 2 outputs Flyback DC/DC converter based on UCC28700. The design is based on reference design PMP10415, but with lower input voltage (300-400 VDC). I have attached the schematic. The two outputs are targeted to deliver 30W each at 15V. The transformer has 60 turns on the primary, 6 turns on each secondary and 9 turns on the auxiliary output). We have tried two primary inductance values: 300uH and 500uH. The result in both cases is an unstable behaviour, with the duty and frequency moving, even with occurences of time slots with no swithcing. (The test was performed at 400V input).The only way to get a stable behaviour so far is replacing the sense resistors (2 x 0.39 ohm in parallel) with a single 1 ohm resistor). But in this way the output power is limited.

What can we try to get a stable working ? Is it possible to have more information on the control law (loop gain, poles and zeros) ?

Thanks.

Regards,

Ottavio DI Sauro.

  • Hi Ottavio,

    Let me ask one of the engineers who worked on the original design to contact you about this issue.

    Regards

    Peter
  • Thanks Peter for your support.

    In the meanwhile we have tried to increase the snubber resistor up to 47K, without any result.

    Since we have three DC/DC on the same DC bus provided with 2x220uF caps (now only two of them are working), we have verified that one of them works fine (lower power 25W) and the higher power (2 x30W) doesn't.

    We have also verified that if we turn off the 25W DC/DC, the 2x30W works much better. But if we look on the scope the signal on the VS pin, we don't see anything wrong.

    Regards, Ottavio
  • Ottavio,

    I am not familiar with PMP10415, but I will try to help you with this.

    First of all, you mention above that you attached the sch, but I don't see it. Can you please attach it?

    You say that there is another 25-W power supply running off the same bus with no issues, does that also use UCC28700?

    When you tested at 400 V, was this DC-input or AC? (trying to establish if bus cap ripple is causing any issues).


    For the dual 30-W supply, I assume the 2 outputs are both 15 V, isolated from each other? So the total power is 60 W?

    for 60:6 turns ratio, the reflected primary voltage will be ~ 160 V, so I assume the primary FET is pretty high voltage rating?

    The 9T aux may be higher than ideal, but it should be ok to start with.

    Assuming that the total output power is 60 W, first step is the choose the correct Rcs value per eqn 23 in the datasheet. For this, we assume the dual 15-V outputs are combined into 1 output that supplies all the power. So for 4 A full load, let's set the CC limit Iocc at say 4.4 A (110% of rated). From eqn 23, assuming 95% transformer eff, and Nps of 10 (60:6), Rcs should be about 0.353 ohm - so the values above are either much too small (2 x 0R39 in parallel) or too big (1 R).

    Once Rcs is chosen, that fixes the max peak current, and for a given target fmax, the required inductance can be calculated from datasheet eqn 25. In this case Ippmax is 0.75/0.35 = 2.14 A. I don't know your target fmax, but it must be less than the datasheet min of 120 kHz. The advantage of maximising Fsw is that it will reduce the inductance and transformer size, and it will also minimise the size of output cap needed for loop stability.

    Let's say your target Fmax is say 100 kHz (you can recalculate for your actual fmax target), then from eqn 25, assuming say 1-V rectifier drop (conservative), Lp = 323 uH - so the 300 uH value you used was close, it will mean a slightly higher fmax about 108 kHz.

    Now we need to ensure that the output cap (total, sum of both 15-V outputs) is large enough to satisfy the voltage loop and maintain adequate phase margin. This is not included in the UCC28700 datasheet at the moment, but there is an eqn 22 in the more recent datasheet for UCC28730 that calculates Cmin = Kco *(Iocc/(Vo * fmax_actual)). For the UCC28700, the recommended Kco factor is about 400. So Cmin = (400 * 4.4 A) / (15 V * 108 kHz) = ~1100 uF. So you would need at least 560 uF on each 15-V output.

    If you are designed for lower fmax and higher Lp, then the Cmin value for stability would be higher.


    Can you double check your design and calculations against the above and see if any of these points might resolve your issue?


    Thanks,
    Bernard
  • Thank you very much Bernard.

    I'll go through all points and check them against the design.

    Regards,
    Ottavio