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Problems about voltage in current sense pin of UC3845 applied in a Flyback converter, using primary side feedback.

Other Parts Discussed in Thread: UC3845, UC3843

Hi,


I have been using UC3845 for a flyback converter, primary side feedback. I have some problems about the voltage in the current sense pin. According to the datasheet, the voltage can be 1V for maximum. However, voltage of the current sense pin of my prototype can only be 0.4V for maxmum!  Some ringing happens in the pin. I don't konw if this is the reason.

Here is the detailed information

I started from a light load. The voltage in the current sense pin is very low, and the converter worked very well. Then I increased the load, the peak voltage in the current sense pin increased as well. Before the peak voltage of the current sense pin reached 0.4V, the converter worked well all the time. After that, when I increased the load. The voltage pin in the "comp" pin achieved it's maxmum, about 7V. The control loop broke down!

Thanks!

  • Hi

    In order to help resolve your problems, can you give me some more details?

    Can you show the sch with values, plus transformer inductance and turns ratios?

    What is the input voltage range, output voltage, and power level?

    When you say that you are using primary side feedback, can you explain? Are you regulating from the primary side aux/bias rail?


    Thanks,
    Bernard
  • Dear Bernard,

    Thanks for your attention! Here is the specific information.

    Input: 12V; Output:23V 4 outputs, totally 15W.

    Transformer:

    Primary Inductance: 6.77uH, Np:Ns1:Ns2:Ns3:Ns4:Nfb=9:23:23:23:23:23

    The schematic is as follows:

    Output capacitor is two capacitors in series.

    Thanks again!

  • Unfortunately, I cannot see the schematic. It most be attached using the "insert file" or "attach from Word" buttons in rich Formatting editor. Windows cut&paste does not work.

    I cannot tell further without knowing the sch values for the current sense resistor and the osc freq. But the primary inductance is quite low, the di/dt of the current will be high.

    But if the CS shunt value is very small, then the signal at the CS pin may not be able to reach the 1-V threshold before the PWM hits the 50% Dmax limit. This could explain why it only gets to ~0.4 V before the output loses regulation.

    Thanks,
    Bernard
  • Sorry for replying after such a long time.

    Above is my sch. I have seen the duty cycle when the voltage of comp pin changed to its maximum suddenly. I tested this by feeding the comp pin trough  independent power supply. It's the PWM hitting the Dmax limit that cause the problem. 

    I don't know UC3845 limit the duty cycle of which to 0.5. My maximum duty cycle of the drive signal can not hit 0.5. Here is the phenomenon:

    From 1 to 3, the signals are 1. signal in current sensn pin, 2.signal in comp pin(I set this a little higher to make sure the duty cycle is maximum), 3. signal of the output pin(drive signal).

    It seems like that the duty cycle of the current sense pin can hit 50%. While the duty cycle of the drive signal can not hit 50%.

    Is this the normal phenonmen?

    Thanks!

  • Neil

    My apologies for the delay in responding, I was out of the office due to illness.

    In the scope plots above, it can be seen that the CS pin is reaching ~0.5 V at the end of the cycle. This is consistent with the ~2.5 V level on COMP. Internally, there is ~1 V offset and then 1/3 divider between COMP and CS. So CS peak = (COMP - 1 V) / 3 = (2.5 - 1) / 3 = 0.5 V.

    It can also be seen from the CS waveform that the converter is running in CCM. What is the input voltage for this test? What is the output load power? In CCM, the duty cycle is limited by the input voltage and transformer turns ratio. [Vo*(Np/Ns)]/Vin = D/(1-D). If you want to stay below D = 0.5 at Vinmin, then reflected Vo (i.e. Vo*(Np/Ns))must be less than Vinmin.

    From your sch, the RC value should set the freq to ~ 500 kHz (f = 1.72 / (R *C)) from datasheet. However, clearly the actual freq is more like 250 kHz. This is because the UC3845 version is limited to 50 % duty cycle, this is achieved with an internal toggle flip-flop that skips every second cycle.

    As seen above, the converter is running close to max capability, i.e. even though the CS pin is a long way from the 1-V maximum, it's right at the 50% Dmax. Any increase in load or decrease in Vin will cause the Dmax limit to take effect, Vout will fall out of regulation, COMP will keep on rising, but to ne effect, and will eventually clamp at its max level.

    I would suggest that you should re-check your power stage design and calculations (mag inductance, Np/Ns ratio, Rcs value) and maybe make some changes if you still cannot deliver full power at Vinmin.

    Alternatively, you might consider switching to the 100% duty cycle version in the family, UC3843. However, I still recommend double-checking the power stage design calculations.


    For your final question, the duty cycle of the CS appears longer than OUT because of the turn-off delay of the external FET Q14. There is a 47-ohm turn-off resistor, so depending on the size of the gate capacitance, there will be a delay as this cap is discharged before the FET turns off, so the current will keep flowing a little longer until the FET actually turns off, a little later than the OUT command.


    I hope this helps answer your questions. If so, please click the green "verify answer" button.


    Thanks,
    Bernard
  • Hi, Bernard

    Thank you for such a detailed answer.
    I have checked my design and found my problem. The maximum duty cycle is too close to the limited value.

    Thanks again,
    Neil