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Buck PFC control with UCC28180, explanation needed to understand the operation of ICOMP

mechaniK
Prodigy 180 points
Other Parts Discussed in Thread: UCC28180, TIDA-00652, TIDA-00443

Hello TI support team,

My question is in relation to the Design guide http://www.ti.com/lit/pdf/tiduas3.

On Page 9, under section 4.5

"The UCC28180 is a boost PFC IC by design; however, the flexibility offered by the IC makes it easily adaptable to control a buck PFC topology. This adaptation is possible by bypassing the current loop by placing a Zener-based constant voltage source at the ICOMP pin of the UCC28180 device. The user must be careful to ensure that the potential of the ICOMP pin is kept above 3 V"

1. Why does the current loop is bypassed ? Don't we need current loop compensation in Buck PFC or I am missing something?

2. And what happens when the current loop is bypassed and a zener of fixed value acts as a voltage source at ICOMP pin.

3. How  does the sinusoidal shape of current is preserved in this case?

4. Irrespective of harmonic distortion or EMI complaince to IEC directives, can we use this buck topology using UCC28180 for power levels upto 1kw?

Thank you,

Abhishek

  • 0
    TI__Genius 9130 points
    Abhishek,

    These are very valid questions and concerns.

    I will contact the original designer of this TIDA-00652 and get some responses to your questions.

    Thanks,
    Bernard
  • 0 in reply to Bernard Keogh
    Prodigy 180 points
    Hi Bernard,

    Awaiting Answers !

    Regards,
    Abhishek
  • 0 in reply to mechaniK
    TI__Genius 9130 points
    Abhishek,

    I have been in contact with the original design team, I am awaiting feedback from them. I will post it as soon as I get it.

    Thanks,
    Bernard
  • 0 in reply to Bernard Keogh
    Prodigy 180 points
    Dear Bernard,

    30 Days gone and guys at TI think that the customer will keep on waiting endlessly. I hope that the design team behind TIDA-00652 is still with TI or was it outsourced job work from whom you are unable to get any explanation ?

    regards,
    Abhishek
  • 0 in reply to mechaniK
    TI__Genius 9130 points
    Abishek

    My apologies for the continued delay.

    As it happens, the original designer of TIDA-00652 had already left TI before you posted your question. But I have asked that team for a response to your question, and I have sent reminders.

    I will follow up with them again to try to get an answer for you.

    Thanks,
    Bernard
  • 0
    TI__Genius 9790 points

    Hi, Abhishek

    Regarding to your four questions:

    1. placing a zener-based constant voltage source at the ICOMP pin would bypass the current loop. In Buck PFC, only voltage loop is fine to control buck PFC. in this reference design, there is no current loop compensation.

    2. Inside UCC28180, duty is defined by ICOMP and VRAMP. If current loop is bypassed and ICOMP is constant, so the duty is only defined by VRAMP. VRAMP is defined by VCOMP, so the duty is only defined by voltage loop.

    3. First, please refer to attachment I attached here. in one AC cycle, the duty cycle would be constant, when AC is high, the input peak current is high, so the average input current is sinusoidal. please refer to the Figure6 and figure 7 in this reference design.

    4. for 1KW PFC, buck topology is not the right solution, you should select to Boost PFC with UCC28180, which is better for THD and EMI. TIDA-00443 is a good reference design for BOOST PFC at 1kW power level.

    Multiplierless PFC Operation.pdf

    Regards,

    Yunsheng 

  • 0 in reply to Yunsheng Qu
    Prodigy 180 points

    Hi Yunsheng,

    Thank you for the much awaited explanation. The application note on multiplierless operation was very informative.

    But the 4th point still needs a bit of clarification,

    If we IGNORE the EMI pollution or harmonic ingress caused by the poor THD response of buck PFC topology is there any other factor which hampers or makes it difficult to use buck pfc at +1kw power levels technically, provided the devices used for switching such as mosfets and diodes are adequately rated ?
    My criterion doesn't take the EMI and THD into consideration at this moment. Hence I want to know what other factors are there which may pose a threat in using buck pfc at high power levels other than THD/EMI ? If any


    Thanks to Bernard Keogh for making this discussion fruitful.

    regards,
    Abhishek 

  • 0 in reply to mechaniK
    TI__Genius 9790 points

    Hi, Abhishek

    At such 1000W application, I did not see Buck PFC is selected.

    First, the input current of Buck PFC is not continuous, which increase peak voltage stress of MOSFET of Buck convert. You need much higher current level MOSFET than Boost PFC.

    For a real PFC, you cannot ignore EMI and ITHD. The higher input peak current makes EMI filter is harder to design and charge more cost.

    Due to the inherent voltage step down characteristics, the buck converter can’t shape the input current when input voltage is lower than the output, it has a higher THD and lower power factor compared to the conventional boost PFC. 

    Regards,

    Yunsheng 

  • 0 in reply to Yunsheng Qu
    Prodigy 180 points
    Hi Yunsheng,

    Thank you for the reply,

    What if the mode of operation selected in Buck PFC is CCM from moderate to heavy loads ?

    regards,
    Abhishek
  • 0 in reply to mechaniK
    TI__Genius 9130 points
    Abishek,

    The Buck PFC has an advantages over the Boost PFC if you need to maintain a relatively flat eff curve vs input AC line. The Boost suffers from a very significant drop in eff at low line 90 V ac when boosting up to ~400 V dc bus; but the Buck PFC does not suffer so badly, and the high eff can be maintained a lot better at low line.


    However, as Yunsheng mentioned, if PFC/harmonic current limits apply (some spec must apply, otherwise why is PFC needed in the first place?), there will be an upper limit on the power level capability of the Buck PFC - this is because of the dead-time/cross-over distortion near the AC zero-crossings, when the instantaneous AC input voltage is lower than the DC bus output voltage. This limits the achievable THD and PF, depending on the chosen bus voltage level and the control IC current loop performance and the shape of the line current. More rounded pseudo-sinusoidal current will have lower higher freq harmonics, but will have a lot more 3rd and 5th, which will limit the power level. On the other hand, a more "square" current shape will have higher PF and less 3rd/5th harmonic, but may fail the IEC harmonic current limits at higher frequency harmonics.

    Since IEC6100-3-2 has an absolute upper limit on harmonic current (class A equipment), this usually limits the Buck PFC to an upper limit of about 500 W, depending on the line current wave-shaping that is used.

    However, even at less than this power level, there are many practical downsides of the Buck PFC that could render it not feasible:
    - input lightning DM surge management
    - size of bulk cap, since bus voltage is much lower, energy storage eff is much less, bulk caps must be larger
    - higher bulk cap % ripple due to inherent AC cross-over dead-time
    - protection of bulk cap during fault if buck PFC FET fails short, or other bus overvoltage situations
    - high-side FET drive required if the output bus voltage must be GND-referenced
    - if low-side FET is used, then the buck output bus voltage is floating, requiring high-to-low side sensing cct for voltage loop regulation


    This paper from the 2010 TI Power Supply Design Seminar has a lot of detailed info about the Buck PFC, including the advantages and the practical difficulties:
    http://www.ti.com/lit/slup264


    In short, I would agree with Yunsheng, at 1-kW power level, the boost PFC is probably a safer and easier option.


    I hope this answers all of your questions, if so please click the "verify answer" button.

    Thanks,
    Bernard