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UCC28950 issue

Other Parts Discussed in Thread: UCC28950

Application:DC/DC Converter

Design Parameter

Input Voltage:200~430V

Output Voltage:9~16V

Maximal Output Current :160A

Transformer Ratio, Primary:Secondary:  11: 1:1

Switching Frequency:100kHz

Topology:

 

Issue Description:

   The  ripple Voltage of output is too high(Vpp=1V),to exclude the close-loop affection,customer to make UCC28950 run in open loop by clamp the voltage in COMP to 2V。but, the Vpp voltage is still too high,below is the comp voltage and primary side voltage:

Yellow:Vout  Green:COMP  Blue:Primary side voltage

 

The waveform shows that there is a jitter under 500kHz frequency, there is no jitter in COMP voltage, 

  

above waveform shows that the duty cycle is not stable

 

Above waveform test condition

Vin=300V

Vout=10.9V

Iout=120A

 

below is the UCC28950 schematic

 

  • Hi Eason,

    Can you clarify the waveforms plots in the post. Which channel is the COMP pin voltage, is the green waveform ?

    It may take a day or two to reply in more detail.

    Thanks

    Peter
  • Hi, Peter

    Yes, the Green waveform shows the COMP voltage.

  • Hi, Peter

    Any feedback please?
  • Hi Eason
    Some customers have seen increased jitter when operating at close to 40% duty cycle which is about where your design is running. Try putting a resistor from SYNC to GND (try values between 10k and 800k). This has been successful in other cases.
    Also check that there is no unwanted coupling between the PCB traces at the SYNC and CS pins – this is critical because the SYNC line carries a digital clock line, the edges of which can couple noise onto the CS signal and cause the PWM comparator to terminate the cycle early. This interferes with the correct operation of the feedback loop and can cause jitter.
    As regards the lower frequency oscillations – it’s unclear to me what the horizontal scales are so I can’t figure out the frequencies of the instability. It may be that the higher frequency instability is due to the jitter. The lower frequency instability might be a loop phase margin issue but I’d need to know what the frequency is.
    Let me know how you get on
    Regards
    Colin
  • Hi, Colin

    I have already put a 10k resistor from SYNC to GND, but it seems not the cause.
    I'd like to show some PCB layout to you and it may need your help to check, may i have your mail address?
  • Hello Eason

    Please send the files to me at colingillmor@ti.com

    I'd prefer to receive Gerber files - of course these files will remain confidential and will not be shared with anyone outside TI.

    Regards

    Colin