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UCC25600 questions about datasheet

Hello,

I got following questions from customer.

Coulc you please put answers for those?

===============================================================================================

Q1) In page 1, there is a following description, but not mentioned in Electrical Characteristics parts in the datasheet.
“ Integrated Gate Driver With 0.4-A Source and 0.8- A Sink Capability”
Is this guaranteed specification?

Q2) In Table 1, DT port explanation, it says 
“To prevent shoot through when this pin is accidentally shorted to ground, the minimum dead time is set to 120 ns. Any dead time setting less than 120 ns will automatically have 120-ns dead time.”
  Is this 120-ns guaranteed value?
  Can you show min/max value for this period?

Q3)Regarding to SS capacitor, 1uF is defined as recommended maximum capacitor.
  In customer's application, longer soft start period will be required and more capacitor is required than 1uF.
- Is 1uF actual maximum capacitor for correct operation?
- Why maximum capacitor is defined as 1uF?

Q4) Regarding to “FSW(start)”, is this fixed value and user can not configure this value?

Q5) Regarding to “GATE DRIVE” specification, GD1, GD2 output voltage high is specified as 9V(min) to 11V(max).
  Is this defined under the condition of VCC being between 11V and 18V?

Q6) “Thermal shutdown threshold” is defined as 160deg(typ), but absolute maximum ratings for Tj is described as 125deg.
  Why thermal shutdown is defined as 160deg which is far above Tj max?

Q7) Customer wants to set switching frequency as 290kHz.
According to equation (18), required IRT will be
                           IRT = 290[kHz]/83[Hz] = 3.493mA
To get IRT of 3.493mA, RT resistance would be,
                     RT resistance = 2.5V/3.493mA = 0.715kohm.
- Is it correct understand?
In this case 0.715kohm is smaller than 1kohm, which is smaller than recommended RT resistance.
- What is the concern when using RT resistance under 1kohm?

Q8) What is OC_latch? Could you provide explanation for this?
Would OC_latch be connected to FAULT block in Block Diagram?

Q9) In section 7.3.1, it says "During soft start, the switching frequency is increased."
  With followings, this expression makes the customer bit confusing.
- From Figure 12, switching frequency looks like decreasing during soft start.
- And Start frequency is fixed at 142.5kHz with regardless with RT resistance.
Is this based on the assumption that operating switching frequency is typically higher than 142.5kHz?

========================================================================================

Best Regards,

Nobuo Fujihara

  • Hi Fujihara-san,

    Can you give us a few days to run through the list of questions in the post ?

    Thanks

    Peter
  • Q1) In page 1, there is a following description, but not mentioned in Electrical Characteristics parts in the datasheet.
    “ Integrated Gate Driver With 0.4-A Source and 0.8- A Sink Capability”
    Is this guaranteed specification?

    No. This is typical numbers. We can't measure the peak current during the test. The gate driver is tested based on the on resistance and the rise fall time as shown in datasheet page 6 GATE DRIVE section

    Q2) In Table 1, DT port explanation, it says 
    “To prevent shoot through when this pin is accidentally shorted to ground, the minimum dead time is set to 120 ns. Any dead time setting less than 120 ns will automatically have 120-ns dead time.”
      Is this 120-ns guaranteed value?
      Can you show min/max value for this period?

    I need to check with test engineer and find that out

    Q3)Regarding to SS capacitor, 1uF is defined as recommended maximum capacitor.
      In customer's application, longer soft start period will be required and more capacitor is required than 1uF.
    - Is 1uF actual maximum capacitor for correct operation?
    - Why maximum capacitor is defined as 1uF?

    The  recommended maximum SS capacitor is to consider the internal discharge circuit current handling capability. If you need longer soft start time, you can either parallel a resistor with the capacitor to bypass some soft start current or use extra diode and capacitor to make your own soft start and then discharge the big capacitor through other means

    Q4) Regarding to “FSW(start)”, is this fixed value and user can not configure this value?

    The start up frequency is ~100kHz above your minimum switching frequency setting. It changes with your minimum switching frequency setting

    Q5) Regarding to “GATE DRIVE” specification, GD1, GD2 output voltage high is specified as 9V(min) to 11V(max).
      Is this defined under the condition of VCC being between 11V and 18V?

    No, it is only for 11V . There is no voltage clamp of this driver.

    Q6) “Thermal shutdown threshold” is defined as 160deg(typ), but absolute maximum ratings for Tj is described as 125deg.
      Why thermal shutdown is defined as 160deg which is far above Tj max?

    The minimum value for the thermal shut down needs to be above 125 so that we can guarantee the 125

    Q7) Customer wants to set switching frequency as 290kHz.
    According to equation (18), required IRT will be
                               IRT = 290[kHz]/83[Hz] = 3.493mA
    To get IRT of 3.493mA, RT resistance would be,
                         RT resistance = 2.5V/3.493mA = 0.715kohm.
    - Is it correct understand?
    In this case 0.715kohm is smaller than 1kohm, which is smaller than recommended RT resistance.
    - What is the concern when using RT resistance under 1kohm?

    There is no concern on RT resistance small. However, the part  enters burst mode operation at 350kHz with minimum value of 300kHz. Operate at 290kHz gives very little room to operate

    Besides, the RT is to set up the minimum switching frequency at lowest input voltage and maximum load. The normal operation frequency is demanded by the feedback loop

    Q8) What is OC_latch? Could you provide explanation for this?
    Would OC_latch be connected to FAULT block in Block Diagram?

    When the CS pin goes above 2V typical, IC latches off, You need to recycle VCC to release the latch

    Q9) In section 7.3.1, it says "During soft start, the switching frequency is increased."
      With followings, this expression makes the customer bit confusing.
    - From Figure 12, switching frequency looks like decreasing during soft start.
    - And Start frequency is fixed at 142.5kHz with regardless with RT resistance.
    Is this based on the assumption that operating switching frequency is typically higher than 142.5kHz?

    As mentioned earlier, the soft start makes the startup frequency about 100kHz above the minimum switching frequency. The soft start pin work this way. The lower the SS pin voltage, the more it increases the switching frequency. At beginning, the SS pin voltage is low, so it increases the frequency a lot. Later, when the SS pin voltage becomes higher, it increase the frequency lower. So it appears the frequency is reducing. In reality, it is just decreasing the extra switching frequency it added

  • Q2) In Table 1, DT port explanation, it says  

    “To prevent shoot through when this pin is accidentally shorted to ground, the minimum dead time is set to 120 ns. Any dead time setting less than 120 ns will automatically have 120-ns dead time.”

     Is this 120-ns guaranteed value?

     Can you show min/max value for this period?

    After checking, the 120ns is not a tested value. This value should be based on the design and not a guaranteed value.

  • Hello Lu-san,

    Thanks for your dedicated reply.
    Regarding to Q4), let me confirm whether my understanding below is correct..
    Q4-1)
    According to equation (2), switching frequency within soft start period is defined by IRT and Vss.
    At Vss = 0V and IRT=0mA, equation (2) shows the highest frequency, and I assume this is FSW(start).
    At 6.5 Electrical Characteristics, Fsw(start) is defined as 142.5kHz as typical value, this frequency came from IRT=0 and Vss=0.
    Is this correct?
    Q4-2)
    Customer would like to set switching frequency as 290kHz.
    In this case, switching frequency during soft start period exceeds 300kHz and almost reach to 400kHz.
    Is there any concern to enter burst mode?
    Q8-1)
    Also for answer for Q8), what is the device latched off status?
    - Gate drvier is pulled down.
    - Switching frequency is stopped.
    - Recoverd only when VCC rise from UVLO
    Is this corrcet?
    Best regards,
    Nobuo Fujihara
  • Please see my comments below in red

    Thanks for your dedicated reply.
    Regarding to Q4), let me confirm whether my understanding below is correct..
    Q4-1)
    According to equation (2), switching frequency within soft start period is defined by IRT and Vss.
    At Vss = 0V and IRT=0mA, equation (2) shows the highest frequency, and I assume this is FSW(start).
    At 6.5 Electrical Characteristics, Fsw(start) is defined as 142.5kHz as typical value, this frequency came from IRT=0 and Vss=0.
    Is this correct?
    No. There should be resistor on the RT pin during this test. The test condition is removed by mistake. The resistor on RT pin should be 4.7kohm.
    Q4-2)
    Customer would like to set switching frequency as 290kHz.
    In this case, switching frequency during soft start period exceeds 300kHz and almost reach to 400kHz.
    Is there any concern to enter burst mode?
    No. The burst mode is disabled during soft start
    Q8-1)
    Also for answer for Q8), what is the device latched off status?
    - Gate drvier is pulled down.
    - Switching frequency is stopped.
    - Recoverd only when VCC rise from UVLO
    Is this corrcet?
    all of above. This is correct
    Best regards,
    Nobuo Fujihara