UCC28950 : OUTC and OUTD pulse width issue

Hi Yoshwa,

I have asked the engineer that supports the UCC28950 to respond to your post, I know he is busy today with internal training so it may be tomorrow before he can respond.

Regards

Peter

Customer schematic is attached.

UCC28950 schematics.pdf

PWM errors are occurred to OUTC and OUTD for all load condition between small 100W to full 1100W load.

OUTA and OUTB are no problem.

 

Hello Yoshwa-san

You are correct that there is a similar issue at DMAX when the UCC29950 is operating at current limit. In your case the system seems to be operating at Dmax but not at the current limit point and I think the problem is due to noise coupled onto the CS pin during switching which terminates the 'missing' cycle  immediately it starts.

Could you send me the PCB Gerber files and I'll review them to see if there are any things we could suggest to help diagnose and solve this issue ?  You can send them to me directly at colingillmor@ti.com - they will of course be treated as confidential information and won't be shared.

BTW

Is this the same issue as the one at https://e2e.ti.com/support/power_management/isolated_controllers/f/188/p/559357/2047634#2047634 ?

Regards
Colin

Hi Colin-san,

Thank you for your answer.

I sent an e-mail.

Is it difficult to correspond by changing schematic?

Best Regards,

Kuramochi

Hello Kuarmochi-san

Thanks - I received the schematic. I don' think that this is just a schematic related problem, it's much more likely to be PCB layout related or possibly the 'Triple pulsing' issue that we have seen in the past.
The filtering at the CS pin is 1000pF and 1kOhm - this looks reasonable but the effectiveness of this filter is extremely dependent on the positioning of the components and the layout (they should be placed as close as possible to the CS pin on the IC with a very short GND returne path.

Regards
Colin

Colin-san,

Thank you for your help.
I'll send you the PCB layout as soon as I get it.

And I posted a wrong thread...

Best Regards,
Kuramochi

Colin-san,

Unfortunately, my customer can not submit the layout with their compliance.
So could you tell me important point as PCB layout?

Best Regards,
Kuramochi

Hello Kuramochi-san

Not being able to see the layout makes it impossible to offer any good advice. Any customer PCB layouts I receive are treated as customer confidential information and are not shared - even with my colleagues.

I'd suggest that the customer probe the waveform at the CS pin of the controller and look for noise spikes which may cause the PWM comparator to trip incorrectly.

Noise can be coupled onto a line through E field or H field. E field is more common and is due to stray capacitance coupling a signal with a high dv/dt from another track. So - the general rule is to look at all the pcb tracks near the CS signal path (on all layers of the PCB) and reroute any lines that are carrying high dv/dt signals. Ground planes can also be used to divert the capacitively coupled signal away from sensitive lines like the CS pin into a local ground. The RC filter used on the CS signal MUST be placed AT the CS pin with a good (ie short) connection to the GND. The decoupling capacitors at VDD must also be connected DIRECTLY at the VDD pin - again with a good connection to ground. Signals like the OUTx signals, the SYNC lines and any of the nodes in the power train which are being switched. All of this is just general advice - without being able to see the layout I really can't help much more.

Do let me know if I can help any further - I'd be interested in seeing the waveform at the CS pin.

Regards
Colin