What is the minimum required sync pulse width and amplitude for synchronization on the UCC28C43D pulse width modulator?
Thanks for your help with this!
Richard Elmquist
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What is the minimum required sync pulse width and amplitude for synchronization on the UCC28C43D pulse width modulator?
Thanks for your help with this!
Richard Elmquist
Bernard,
The customer has come back with additional questions. I am not sure that you will be able to answer them,. but here they are:
For this application of the UCC28C43D we are investigating potential noise pulses levels retriggering the sync.
We would like to know how much design margin we have to the 1.6Vpp level and the 50 nSec width.
Are these the absolute numbers or would you recommend some % of design margin to ensure not re-triggering the sync due to noise?
What is the process tolerance for this voltage level and pulse width in the PWM chip?
Would it be likely to change from lot to lot of parts?
We are just trying to quantify the absolute requirements for voltage and pulse width that will trip the pin3 CS and re-clock the pin 4 RT/CT .
Through the use of filtering we are alleviating the noise but we need to know how much margin we can live with based on the absolutes for those pins.
Can you comment on any of these questions?
Thanks for your help with this!
Richard Elmquist