Other Parts Discussed in Thread: LM8364
Hi,
we have an application where the LM5030 has to be Power-ON with outputs disabled(ie No PWM at Out1 and Out2).
At the same time, soft start capability of the LM5030 should be able to use when it is enabled.
For this, we plan to drive the 'SS pin' from the GPIO of uC/FPGA. GPIO is a normal one, not an open-drain pin.
It can't ensure that GPIO will be at Ground during initial Power-ON or during Reset.GPIO may be at high impedance state during Power-ON or during reset.
But it has to make sure that LM5030 is not turned on when GPIO is at high impedance or ground during Power ON or Reset.
LM5030 outputs have to enable only when only when GPIO is at logic high(3.3V). Along with Soft-start timing requirement of 2seconds also have to meet once LM5030 is enabled.
Question1. Please give me some suggestions for implementing the circuits to realize the above requirement?
Thanks in advance
DEEPAK V