UCC28950: controller validation / open loop operation

Hello Samrat

Your circuit looks fine except that the 10k resistor from SYNC to GND is not necessary. This method should indeed allow you to run the device open loop, you may have to adjust the voltage at the EAP pin - try a 20k potientometer from VREF to GND.

I'd suspect that the device is either damaged or else not connected correctly. The VREF is a basic function of the IC and it should be correct under all circumstances where VCC is ok. Double check the connections - especially VCC and GND. If you can, I'd just replace the controller if there is any doubt about the connections. It's very easy to damage an IC if the GND connection is missing for example.

Regards

Colin

Hello colin

rechecked everything but couldn't find the problem.!

I suspect that voltage at pin DELEF is (-1.99) which is outside the absolute allowable maximum ratings limits at the pin. but then the resistor used is in range allowed. so what i am missing ? Also SYNC pin is producing pulses of same amplitude as the VDD, is that normal?

Can you suggest me any other configuration to validate the open loop operation?

thanks and regards
samrat

Hi Samrat

Firstly, the SYNC signal amplitude should be 0 to Vref - it definitely shouldn't reach VDD. Are the SYNC pulses at a constant frequency and does that frequency correspond with what you expect from the value of RT ?

DELEF = -1.99V is very strange. This is well outside the Abs Max rating of the pin (-0.4V) and I would not expect the IC to survive an overvoltage of that magnitude.

The bigger question is where is the -1.99V coming from - I don't see any voltage less than 0V in your schematic. I'm sorry but that definitely points to an error in the build somewhere. I'd start with the GND pin and see if it is at the same voltage as the -ve input of the VCC supply - bear in mind that the voltage you are interested in is the one on the metal of the IC leg - not the voltage at the PCB pad - you may have an open circuit somewhere.

As regards validating open loop operation - I think that if you can get your existing board to work then it should be a good test configuration.

Let me know how you get on.

Regards
Colin

hello colin

please check this simulation file

open_loop_validation.TSC

results are

In simulation itself overvoltages at DELEF and SYNC pin. How to rectify this issue?

thanks

samrat

Hi Samrat

Interesting !.  So, I ran the sim file you sent and of course I get the same results as you did. A few things - VCC is 8V in the sim so this is why the OUTx signals are 0 to 8V. The SYNC signal is also 0 to 8V but this is not correct. I checked on a UCC28950 EVM here and SYNC is 0 to VREF on the hardware.

On the hardware, DELEF pin is at 2.5V with a 71.5k resistor. There is no physical reason why it could be at -1.99V. I also measured 230mV at DELCD (15k to gnd) where the sim is showing 123mV with either 15k or the original 78k. but I think that the actual delays produced between the AB and CD transitions are present.

I'll pass your observations on to my colleagues in the group responsible for this model but in the interim my advice to you is to not worry too much about about them and concentrate on the OUTx signals and their behaviour.

Please double check your hardware - the DELEF pin in particular should be at a positive voltage - like I observed here on the EVM.

Please let me know how you get on.

Regards

Colin

hello colin

I tried doing same pin voltage measurements on the oringinal simulation slum276 reference as

slum276 (3).tsc

and again found the same results there also SYNC pin and DELEF pin.

some pins are staying at the same voltage despite changing the the connected resistor. so I believe that the transient model has some limitations it seems or not exact ? If you get to know about the limitations please let me know. so shall i proceed with the hardware without worrying about this abnormal simulation voltages at pins?

thanks for the support

samrat