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UCC27712: The conditions for Interlock operation

Hidekazu Someno
Expert 5130 points
Part Number: UCC27712

Hi team,

 

My customer has an inquiry about interlock operation.

 

At Section 8.4.2 in UCC27712 datasheet, there is the following description.

“The UCC27712 generates a fixed minimum dead time of tDT which is 150ns nominal in the case of LI and HI overlap or no dead time.”

 

What are the conditions for "in case of LI and HI overlap or no dead time"?

How long is the criteria of “no dead time” between LI and HI signals that this IC starts “INTERLOCK” operation?

 

Best regards,

Hidekazu Someno

  • 0
    TI__Guru**** 189399 points

    Hi Someno-san,

    Great to hear from you!!! A couple years ago, I transferred to the High Voltage Products team!

    If you look at Figure 29 in the d/s, there is a block labeled, "Shoot Through Prevention." Basically, if this block detects HI and LI high at the same time, it inserts the 150 ns (nominal) dead-time. If HI and LI have less than 150 ns of dead-time, then the outputs are shifted to have 150 ns of dead-time. For example, if the input dead-time is 50 ns, then the output will be shifted to have 150 ns of dead-time.

    Let me know if this isn't clear.

  • 0 in reply to Don Dapkus
    TI__Mastermind 28960 points

    Hello Someno-san,

    I am an applications engineer supporting this part. I want to clarify the interlock behavior. Whenever the input signals have less than 150ns of dead-time, the UCC27712 interlock circuit ensures that there will always be at least 150ns typical of dead-time on the outputs. See the table below:

    Input Dead-TIme Output Dead-Time
    <0ns (both inputs high) Outputs held low
    >0ns AND <150ns 150ns typical
    >150ns Same as input dead-time

    Regards,