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UCC28180: distorsion of the PFC coil current and voltage

Part Number: UCC28180
Other Parts Discussed in Thread: TIDA-00443,

HI,

we are currently working on the TIDA 00443 PFC. while testing we observed some undesirable Vsense and Isense Waveforms. herewith i attached the respective waveforms for your reference.

test condition:

Fixed Output Boost PFC configuration 

input AC 187V

output DC 200V

output current 0.92A

waveforms without mosfet

vsense and input current

Isense

dc input

 

schematic diagram (Isense &Vsense)

1. Why the Vsense waveform is not identical to the output DC voltage waveform? what is the reason for that spike?

2.  What is the reason for the Positive Isense waveform?

also we observed that, after few minutes Isense and Vsense pins goes to some negative values like -320mV or -200mV (without input power). herewith i attached that waveforms also.

Vsense (without input)

Vsense (input ON)

Isense( without input)

Isense (input ON)

now the Isense Looks like a positive and negative half cycles. in the previous waveforms it looks fully positive. what is the reason for this? is there any ground issue? then how to resolve the issue?

help us to solve this issues.

thanks

Kalyan

  • Hi Kalyanraj,

    Thanks for your interest in TIDA-00443. Could you confirm your output voltage setting? 200V output is likely too low for 187Vac input (the peak of the line voltage is ~260V which is higher than the output voltage setting). A boost topology is not able to step down its input voltage.

    Best Regards,
    Ben Lough
  • Hi Ben Lough,
    Thanks for your response.
    Input AC rms voltage is 159V. I removed the mosfet, so there is no boost operation here.

    thanks
    regards
    Kalyan
  • Hi Kalyan,

    Could you help me understand the motivation for removing the MOSFET? Without the MOSFET and no boost operation there is no power factor correction.

    Best Regards,
    Ben Lough
  • Hi Ben Lough,
    We already tested with the boost follower mode, but PFC was not working. We observed discontinues gate pulses from PFC controller. We assumed that this is due to the positive Isense and abnormal Vsense signals . So now we are testing the Isense and Vsense signals without boost operation.



    Regards
    Kalyan
  • Hello Kaylan

    A boost converter with a 200V output cannot achieve power factor correction for any ac line voltage greater than 200/sqrt2 - or 141Vac because Vout must always be greater than Vin. Call it 130V to give some margin.

    Can you test the PFC operation at Vin = 120Vrms and let me know what happens 

    A further suggestion would be to return the TIDA-00443 unit to its original configuration - Vout = 385V approx, and confirm its operation at that point.

    Regards
    Colin

  • Hi Colin,

    Thank you for your interest in this.

    herewith I have attached the waveforms which we captured during the PFC operation. 

    output voltage and input current

        

    Vsense and input current

    gate pulses from PFC controller

    Isense and input current

    thanks

    regards

    Kalyan

  • Hello Kalyan

    What was the line voltage and what was the output voltage ?

    Have you tried to run the TIDA00443 with its original output voltage ?

    The reason for the current spikes is almost certainly that when Vin > Vout there is a direct conduction path from input to output through the boost diode. A boost controller cannot prevent this.

    Regards
    Colin
  • Hi colin,

    I will send the waveforms at rated conditions soon. I want to know,
    1. What is the reason for the Positive Isense waveform? ( it should be always negative)
    2. Why the Vsense waveform is not identical to the output DC voltage waveform? what is the reason for that spike?


    regards
    kalyan
  • Hi Kalyan

    Can you send me your schematic please and also can you identify the point you are using as the ground reference for your measurements.

    The CS signal must be negative and the Vsense waveform should be the same as Vout (with a certain amount of filtering due to the capacitor across the lower resistor in the potential divider)

    Regards
    Colin
  • Hi colin,

    herewith I attached the schematic diagram for your reference.

    regards 

    Kalyan

  • Hi colin,

    Now i tested the circuit without output capacitor c4,c5,c18 in open loop.  here i attached the output voltage waveform and Vsense signal.  output is the full rectified DC waveform, but Vsense is not identical to the output voltage waveform.  why the peak is reduced between each half cycles? . I suspect that this could be the reason for the spike in Vsense.

    output voltage without capacitor

    Vsense

    regards

    Kalyan

  • Hello Kaylan

    Your schematic looks OK to me - it follows the values in the TIDA-00443 schematic closely.

    With the potential divider you have here, (1Meg/13k) the controller should regulate VDC_BUS at 390V and the VSENSE pin should be at 5V when the output is in regulation at 390V.

    I can think of no reason why the signal at VSENSE would not follow VDC_BUS closely and certainly there is no reason why the alternate peaks should be high and low as per your screenshot.

    I presume you are using PGND as the ground reference point for all your measurements.

    I know that your schematic shows PGND connected to UCC28180 GND pin, the bottom end of the VSENSE potential divider and the source of Q1 but could you explicitly confirm that these nodes are connected on your PCB.
    I would suggest that you replace the existing UCC28180 device with a new one - just in case it has become damaged.

    What voltage are you putting on the VCC rail ?

    Please verify the VCC rail on the driver IC too

    Can you replace C4, C5 and C18 and then look at the signal a the GATE pin of the UCC28180 and at the gate terminal of the MOSFET - this is to make sure that whatever signal generated by the controller is being delivered correctly to the MOSFET.

    Can you confirm that the switching frequency of the GATE signal is 100kHz (there may be times during the line cycle where this signal disappears but let's not worry about that yet.

    Regards
    Colin
  • Hi colin,

    I checked those ground points, they are well connected in the PCB also. I already removed the UCC28180 from the PCB before removing the output capacitor.

    At present we are not using that Driver IC (U2).Instead we are using the UCC28180 alone with R2 fitted (R24 removed).

    we are using 15V Pcb mount SMPS for VCC. here i attached the VCC waveform also.

    May I know what is the motivation to replace the output capacitors? do you suspect some problem with those capacitors?

    I suspect that the cause for the discontinues gate pulses are due to the abnormal Vsense and Isense signals. is it right?

    I tested the rectifier circuit in general purpose PCB board with the same value of resistance (full bridge rectifier (new part) with same value of potential divider resistance). In this also I observed that alternate peaks goes high and low.

    regards,

    Kalyan

  • Hello Colin,

    we found the root cause for that alternate peak magnitude difference issue. this is due to some problem in the DSO's input earth connection. we tested the board after removing the DSO's earth connection, now the Vsense signal looks fine. here i attached the Vsense ,Isense,Vcc waveform for your reference. This waveforms are captured before mounting the mosfet.

    after testing those signal we tested the board in fixed boost configuration. But unfortunately after few minutes PFC controller IC busted and following components were failed.

    1.Mosfet

    2.diode D3

    3.resistance R11

    4.diode D4.

    we observed the discontinues gate pulse at the mosfet's gate terminal. what could be the reason for this failure?

    fixed boost config test condition:

    Input RMS voltage 210V

    input current 3A

    output voltage 340V

    output current 1.7A.

    this waveforms are captured without mosfet

    Vsense


    Isense


    DC output


    Vcc

    regards

    Kalyan

  • Hello Kalyan

    A PFC stage under development is normally powered from an AC source or else though a Variac and isolation transformer. These sources are both floating of course so they do not have any direct contact to the earth connection of the DSO. I would never recommend the removal of the DSO protective earth connection and would advise you to re-connect the DSO Earth connection and to power the PFC stage from an isolated source during any future testing.

    The asymmetrical waveforms make some sense in the context of the earthing issue.

    Regarding the output capacitors - you mentioned that you had removed them - I meant that you should put the parts you removed back in circuit. They are unlikely to be faulty and need replacing.

    I take it that you have now repaired the damaged board.

    Can you try again ?

    Increase Vin slowly while monitoring the Vgs and Vds of the MOSFET - try to capture a waveform as soon as switching starts and then send it to me.

    Regards
    Colin

  • hello colin,

    I started testing the PFC again. I start with Vsense and Isense signals. Vsense signal looks fine. but i'm not confident with the Isense signal. here i attached the Isense  and input current waveforms under the following test conditions.

    Vin AC 260V

    Vin current 3.22A

    output DC rms voltage: 350V

    output current 1.52A

    Isense and Input AC current (without Mosfet)

    Isense should be a full rectified waveform, correct?. 

    thanks

    regards

    Kalyan

  • Hello Kalyan

    There may be other problems but without the MOSFET the system will not operate as a PFC boost stage. What you are seeing is simply the effect of direct conduction into the output capacitors during the time when the instantaneous line voltage is greater than the output voltage. You get direct conduction from input to output through the PFC diode. The  peak of 260V line is 367V - assuming some ripple on Vout you will see an output voltage of 350V.

    For you to see a sinusoidal input current you MUST connect the MOSFET. In normal operation you should see about 380Vdc on the output of the PFC stage for any AC line voltage from 85V to 264V - I'd suggest you use 120V for initial testing.

    The line current waveform looks like it is detecting and following the current peaks - (If you do a bit of 'eyeball filtering'. What is a little strange is the -100mV (approx) offset. You should be using the GND pin of the controller as the ground reference for your 'scope and it would be worthwhile to check that there is no offset on the channel itself. - what does the channel show when there is no load current (even in your existing arrangement)

    What value of current sensing resistor are you using - is it the one given by the Excel calculator for the UCC28180 device? - please check this carefully because it has a large bearing on the correct operation of the PFC stage (but not as large as the absence of the main switching MOSFET)

    Regards

    Colin

  • Hello Colin,

    I tested the PFC board with Mosfet.  it works in both fixed boost and voltage follower configurations.But we cannot increase the output current beyond 0.4A. Vds max value goes above the rated value (600V).   here i attached the drain to source voltage and input current waveforms.  

    i'm using 21k resistor for R9 instead of 21.5k. Also I using only the internal gate driver for mosfet (UCC27517ADBV -U2 not fitted)

    test parameters.

    input AC rms voltage 210V

    input current 0.7A

    output voltage max 362V

    output current 0.4A

    Vds



    thanks

     

    regards

    Kalyan

  • hi colin,
    May I know the purpose of C26, which is placed across the Mosfet?
    This capacitor is not fitted in Ti design board.

    regards
    Kalyan
  • Hi Kalyan

    The purpose is to reduce the dv/dt at the MOSFET drain. This is sometimes done to reduce the level of conducted EMI signal measured at the input pins. Adding this capacitor increases the switching losses because the energy in the capacitor (1/2 CV^2) is lost on each switching cycle.

    The EMI can also be controlled by improved input filtering, better PCB layout and increasing the value of the gate drive resistor.

    Regards
    Colin

  • hi Colin,
    I have one more doubt regarding the gate resistance value.
    Since we are using the internal gate driver for Mosfet switching, the total gate resistance value is 3.9+ 1.05 ohms. typical gate resistance value of that mosfet is 3.4 ohms. Present gate resistance value looks higher than the nominal value. May i reduce the gate resistance value?
    what could be the reason for the higher Vds Max value at lower output current?

    thanks
    regards
    Kalyan
  • Hi Kalyan

    You should talk to the MOSFET manufacturer about how to optimise the gate drive resistor for a given application and MOSFET device. The values shown in the schematic are a good starting point. Be sure to use resistors that can withstand the current pulses that happen during gate charging and discharging - normally a 1206 size part is a good choice.

    The Vds value should not be a function only of the output voltage not of the output current. There may be an initial spike on the Vds waveform and this may be a function of load current - possibly due to forward recovery effects in the PFC diode. Can you post screenshots of the Vds waveform at high and low load currents.

    Regards
    Colin
  • Hi Kalyan

    What PCB layout are you using - this can have a large effect on the noise / spikes on the Vds.

    The measurement technique is also important - for best accuracy you should use a tip and barrel method - see https://www.eetimes.com/document.asp?doc_id=1273282 for some more details on this.

    Regards

    Colin

  • Hi,
    I faced so many problems while using Active PFC circuit because of noise.
    I tried passive PFC circuit i.e., Valley -fil circuit. Noise came down to 80%.
    Why don't you try valley fil circuit for this low power output circuit..

    Regards,
    A.S.Bhushan