Is it that in order to sync the clock frequency of the LM5021-2, does the sync clock need to be more than twice the clock frequency set by Rset in order to maintain a maximum of 50% duty cycle ?
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Is it that in order to sync the clock frequency of the LM5021-2, does the sync clock need to be more than twice the clock frequency set by Rset in order to maintain a maximum of 50% duty cycle ?
This is a 2 switch forward converter application that will need to be spread spectrum'ed to achieve regulatory compliance plus the noise margin.
It appears that there is something done inside the chip at the LM5021-2's internal clock at its following edge not at my sync time since the LM5021-2 does not maintain 50% or less duty cycle when my sync pulse occurs after half way point of the LM5021-2's naturally set clock cycle. But when my sync pulse is at or sooner than the half way point of the LM5021-2's clock cycle, or my sync pulse is at or greater than twice the natural clock frequency, I have never seen output duty cycle greater than 50%. Could you check on this?