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TPS65150: Power sequence issue

Patrick Chen
Mastermind 8875 points
Part Number: TPS65150

Hello,

           Below is customer panel power sequence spec. of LSA40AT9001. TPS65150 can not meet panel spec. so they need to delay DLY1 and DLY2 timing as below. What delay time we can setup and has any limit by td(DLY1) and td(DLY2) ? Thank you. 

BR

Patrick

  • 0
    TI__Guru 58225 points

    Hello Patrick,

    According to the above picture, AVDD -> VGL -> VGH -> gamma buffer -> interface supply

    TPS65150 can supply AVDD, VGL and VGH and it supplies it exactly in this order. DLY1 and DLY2 can be set to the minimum because these times just need to be above 0ms. You could use the default 10nF caps, but you could use as well smaller ones.

    Best regards,
    Brigitte

  • 0 in reply to Brigitte
    Mastermind 8875 points
    Hello Brigitte,

    Thank you. Do I know DLY1/DLY2 has minimum limit ? Thank you.

    BR
    Patrick
  • 0 in reply to Patrick Chen
    TI__Guru 58225 points
    Hello Patrick,

    The minimum should be no capacitor connected at all. But to be sure that you can change it if necessary, I would recommend to add at least some pads to make sure that you can add a cap if needed without a layout change.

    Best regards,
    Brigitte