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TPS65150: IC Does not start up properly and faults out.

Austin Carter
Prodigy 40 points
Part Number: TPS65150

So I've been working on this IC for far too long. I'm making a development board for a 5" TFT LCD. 

The IC starts up and the 5v buck regulator starts just fine, but VGL only goes to -5v. It then faults out if I have faulting enabled since it never reaches the full -10v. This prevents VGH and Vcom from ever starting as well. I can disable the fault by removing C8 in the schematic below, which I've done, but then VGL just stays at -5v.

So somehow the IC knows that it's not at the full -10v but the system isn't responding. I've gone through two pcbs with the layout, the first was a 2 layer which wasn't laid out very well. The second is a 4 layer with a much better layout but the behavior is the same. I even checked every single component when I made the 4 layer board to ensure I had no faulty parts. I've also tried multiple TPS65150 IC's

I've included my full schematic below and the only difference is C8 was jumped and is no longer there disabling the fault, and I'm using a 2.2uF cap wherever it says 4.7uF. The power requirements are only 20mA for the 5v buck, and 250uA for the -10v line and +15v lines. I also attached some external resistors to simulate the loads so the charge pumps will operate. Is there anything wrong with my schematic? I'm really at the end of my rope with all of the debugging. I'll try to upload a snapshot of the power on sequence later.

8255.schematic.pdf

  • 0
    TI__Expert 8010 points

    Hello Austin Carter,

    Thanks for your enquiry. First the A5vdd rail is generated from a boost-converter not a buck-converter.

    The output voltages of VGH (TP2) and VGL (TP1) and VCOM (TP4-5) are limited by the output voltage of the boost-converter (A5vdd). In the current configuration it is normal that VGL and VGH do not reach its nominal values. The reason for this and detailed explanation how to configure the charge pumps of the TPS65150 correctly, is explained in this Application Note.

    In summary, you will need to add two more extra charge pump stages on both rails (VGL and VGH) to get the voltages you want.

    Regarding the schematic I have view questions/comments:

    • What are the output current requirements for the rails?
    • The delay time of DLY1 and DLY2 is currently set >25 ms. Is that really what you need?
    • The inductance of 22 µH is not recommended, please choose a smaller one in the range of 3.3µH to 4.7µH (refer to table 3, page 23)
    • The output capacitance is quite small, the effective capacitance should be in the range of 10 µF (be careful of the dc-bias from ceramic capacitors

    Best Regards.

    Ilona

  • 0 in reply to Ilona
    Prodigy 40 points

    Thank you so much, that's the info I was looking for. I was thinking there must be something I was fundamentally misunderstanding. So I guess I will need two more stages for the positive charge pump and one more stage for the negative. The application note you linked my to gives my a bad DNS result. I found this one though www.tij.co.jp/.../slva794.pdf. However, it doesn't address multistage negative charge pumps. How would I go about wiring that up? I can't seem to find any examples on the subject. I can use the data sheet schematic examples for the positive. To address your questions. I'm using an Innolux 5.6" LCD AT056TN52-V3

    EDIT: I found another post, by you actually, about how to wire the negative charge pump.

    https://e2e.ti.com/support/power_management/lcd_oled_bias/f/954/t/464609

    To address your questions. I'm using an Innolux 5.6" LCD AT056TN52-V3
    My input is 3.3v that also powers the 3.3v logic levels on the lcd

    Output Requirements:
    AVdd 5v 25mA (I'm using the output from the boost converter here)
    VGH 15v 240uA
    VGL -10v 260uA
    Vcom 0.72-1.12v

    My data sheet for the display does indeed list quite lengthy start up requirements, all values must be greater than the times listed here.
    3.3v VCC -> 20mS -> VGLH -> 5mS -> AVDD -> 5mS -> VGH -> 10mS -> Data

    I'm certain that it could handle faster times, I'm just going by data sheet recommendations.

    I used a 22uH capacitor to consolidate parts. 22uH is for the LED constant current boost converter that is on the same board. That's working fine. But I suppose I could reduce it in the final design.

    The output capacitance is what I had on hand for parts. With such low current output requirements, I thought I could just use them temporarily. Those will be changed in the final design.

  • 0 in reply to Austin Carter
    TI__Expert 8010 points

    Hello Austin,

    Austin Carter said:

     However, it doesn't address multistage negative charge pumps. How would I go about wiring that up? I can't seem to find any examples on the subject. I can use the data sheet schematic examples for the positive. To address your questions. I'm using an Innolux 5.6" LCD AT056TN52-V3

    EDIT: I found another post, by you actually, about how to wire the negative charge pump.

    e2e.ti.com/.../464609

    Yes as described in that thread, you can wire the switching node of the negative charge pump either to the switching node of the boost converter or directly on the DRVN-pin. As the output current requirement is quite low you can easily wire it directly on the DRVN-pin. Same with the positive charge pump. What is the maximum tolerance that you allow for VGH and VGL. I believe that you most probably need to add also one another negative charge pump stage (in the whole 3x CP stages meaning 3x flying caps, 6x diodes) to generate -10 V due to the headroom that the charge pumps requires (depends on the forward voltage drop of the diodes):

    2Stages: VGL(min) = -2xAVDD + 4xVF +0.13 V = -10 V + 2 V +0.13 V = -7.9 V

    Let me know if you have finished the schematic and I will take a look at it.

    Best Regards.

    Ilona

  • 0 in reply to Ilona
    Prodigy 40 points

    I'm bumping up the Vs to 6v as my lcd can take up to 6.5. A little close but this is only a prototype for development and I'm avoiding another board spin. I'm also using this for my diodes which only has a Vf of 0.2. Changing those I should be able to get the desired VGL and VGH with only 1 extra stage on vgl and vgh. Here's my updated schematic.0027.schematic.pdf

  • 0 in reply to Austin Carter
    TI__Expert 8010 points
    Hello Austin,

    Sorry for the delay. Yes I think you have understood the concept of the charge pump configurations now. The schematic looks quite decent, although I recommend to have at least one more output capacitor on AVDD (due to dc bias of ceramic capacitors).

    Best Regards.
    ilona
  • 0 in reply to Ilona
    Prodigy 40 points

    Thank you so much for your help Ilona, after making those adjustments and adding two more stages the voltages for VGL and VGH are perfect. The LCD is working great now!