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TPS65100: Layout Question related to EMI with VQFN-package

Part Number: TPS65100

The customer encounters EMI-problems with TPS65100 using the reference layout for the VQFN-Version recommended in another post in this forum.

In our reference layout the individual GND planes on the TOP-layer for each voltage output are commonly connected by vias/thruhole pin connectors to BOT-layer. There is no so called "GND-copper pour area" on the TOP-layer in the reference design.

In a real-world Display application these individual output voltages will all be connected to one multi-pin connector to the Display. Regarding EMI-behavior, what is the recommended best practice for the GND connection from TPS65100 to this multi-pin connector?

1. Use GND-copper-pour area on TOP-Layer to connect all GND's of all individual output voltages together and also connect the multi-pin connector GND to this GND-copper pour and take into account that all GND-currents running back to TPS65100 will share the same plane (together with a local GND-area on BOT-Layer below TPS65100 to connect all output GND through via's back to TPS65100, minimizing high-frequency current loops)?

2. Use individual GND current path's from TPS65100 output voltages to multi-pin connector and connect them together at the multi-pin connector (without GND-copper-pour; together with a local GND-area on BOT-Layer below TPS65100 to connect all output GND through via's back to TPS65100, minimizing high-frequency current loops)?

Or do you recommend even a completely different solution?