TPS65100-Q1: TPS65100-Q1 suggestion layout

Hello Lawrence,

The layout file link does not work for me. Please send the layout files to display_power_evm@list.ti.com.

Best regards,
Brigitte

Hello Lawrence,

The schematic looks ok to me.
There are 2 minor observations:
- It would reduce the noise sensitivity of the COMP pin, if the resistor and capacitor would be exchanged.
- It can be helpful for EMI design to have a high-frequency capacitor connected very shortly from the cathode side of the boost diode to PGND of the IC. The cap shall be in the range of several pF, but has to be an effective cap at high frequencies. This cap is then a short for the high-frequency noise created by the parasitics on the switch node.

Please clarify if they are not using the VCOM because both components are not populated.

Best regards,
Brigitte

Dear Brigitte,

base on  TPS65100 EVM as below chart , your suggestion is VCOMIN pin  R1/C6/R4 or C3 can reduce EMI?

IF any , Please advise me.

Thanks,

Best regards,

Lawrence.

Hello Lawrence,

Please excuse the inaccuracy. On the COMP pin there is a resistor R7 and a capacitor C11 connected. As you can see in the EVM chart, the resistor is connected to the pin and the capacitor is connected to GND. In the customer design they are connected vice versa and I recommend to connect it like in the EVM.

Best regards,
Brigitte