I'm considering to use a TPS92512 chip to switch it's output to one of three LED branches of different colours (R,G,B) and run a current of 850mA~1A through it.
Schematic is attached. Vo is connected to three branches of LEDs with 3 high power LEDs in each branch in series (7.5 to 11V forward voltage depending on colour) but each branch has a Mosfet switch to ensure only one branch is ON at any time. Current level can be controlled through Analog Iadj pin.
Two concerns I have is:
1. If Vin falls close to total forward voltage of LEDs, driver goes out of regulation. What behavior it will have in terms of how much current it will push through LEDs in that mode? Would Iadj pin be in charge of controlling output current when chip is not regulating? How about PDIM input?
VIN shuold be high enough to drive LEDs but if for some reason (drooping, running below rec spec) it was not, I would like a dimmed and safe operation to ensure LEDs or chip itself not damaged.
2. When Vin falls below certain level, I see periodic negative spikes on PH pin until VIN rises to above a certain level and regulation resumes. Apparently Cboot falls below 2 V:
(Red: Boot, Yellow Vin, Green Vo,Blue Vsense)
Could these pulses be resulting in EMC issues?
3. Accidentally noticed if RT/CLK pin is touched by finger (discharged by touching Ground beforehand) chip blows up in less than a second!!!
Well although this cant happen in normal operation but wondering why is this happening. I can consistently blow up as many chips as I want by this.
I would appreciate any comments.
In reply to Matt Alizadeh:
Is there any way you could share your layout? A poor DAP connection alone could do it for two reasons: The first is if there is little to no connection the thermal overshoot before thermal protection kicks in might cause damage (unlikely but possible in some cases). The second is that if it isn't fully electrically connected (or a high resistance connection) there will be a lot of noise generated and pins can be over-voltaged and/or see negative voltages, both of which can cause damage. This might be your case.
If not then the layout would be the next thing to look at. If the ground connections aren't very good or the routing is not very good you could see significant negative spiking on the PH pin regardless of the diode and that could damage the switch. I would be happy to look over your layout and comment if you want to provide it.
In reply to Clinton Jensen:
TPS92512_Layout B.zipTPS92512_Layout A.zipSorry if my response is duplicating, for some reason I don't see my reply I sent earlier this morning. I thought it might not posted .
Hi Clint and thanks very much for response.
Good point on PAD connection to Gnd and it's effect on thermal performance and also noise susceptibility.
The datasheet says voltage difference on the PAD should be within +/-200mv versus Gnd. If no solder paste or any problem that might be an issue.
On the layout, I have attached two layouts I have and appreciate any thoughts specially on layout A.
The B version seems to be better overall. If you were to rotate the input capacitors so that their grounds tied directly to the grounds of the IC and the current sense resistor it would be pretty good. I would also not have a fill for the current sense trace as that could give you much more area for noise coupling. I would run a single trace to the IC and a single trace to your other current sense circuitry.
The A version looks a bit more problematic. I love your liberal use of ground vias, I always recommend that where possible. But the placement of the grounds could for sure give you some ground errors and spiking on the switch edges. Refer to the layout section of the datasheet. But basically the critical ground locations are the input capacitors, the IC/DAP, the rectifier diode, and the current sense resistor. In this version they are somewhat far apart and again especially the input caps are a ways away. Ideally you tie these grounds as close together as possible, preferably with a good ground plane with plenty of vias like you are doing. You want the switching current loops as small as possible and their ground current return paths as small as possible as well. As it is there are some sizeable loops. On top of that you are running a high impedance current sense trace right near the switching diode and its ground return path so there is potential for noise coupling that could cause issues. In any case I can see the possibility of voltage spikes with this layout, not that they are alll necessarily big enough to cause problems. It may be a combination of layout and not a solid enough DAP connection. Or it could simply be the devices with faster switch rise/fall times are the ones that fail due to larger spikes below ground.
Basically layout could do it and improper DAP soldering could do it, a combination is only more likely. So I would focus on both. There are some layout guidelines in the datasheet and some layout app notes on ti.com. It really helps, a good portion of problems are due to layout. But soldering the DAP sufficiently is also key for almost all devices that have a DAP.
Yeah, it can be hard. You kind of have to catch one when it fails and that is difficult without many iterations, but a "better" board may show borderline spiking that could give you some idea since you know there will be variations from board to board.
As for the quality of the DAP the only way I am aware of (and I have not done it myself, some other group does it) is with x-ray. You can see dark patches where the DAP and PCB connect and it will be much lighter where they do not. I'm not sure if you have this capability or not and I'm not sure who does. But there are probably labs that could do it if you don't. Maybe whoever did the board assembly does. I have seen more than one case where the assembly process has had to be tweaked to get proper DAP seatin.
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