This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

What is the expected gate drive capability of the LM3433 DIMO/DIMR outputs?

Hello,


I am attempting to use the LM3433 dimming circuit with the bypass FET that shunts loop current away from the LED to provide dimming.  I am using off-times of about 500 nsec for this FET at the dimmest settings and finding that this yields rounded-off edges on the gate-source voltage transition.  This makes the dimming performance unreliable.

The FET I'm using has a typical gate charge of 29.6 nC.  I do not see a drive current rating specified for the DIMO/DIMR pins so I was wondering if there was some guidance available or a recommended setup.


Thanks,
Arthur

  • I still did not receive a spec from TI on the gate drive current of this output. I did learn that my circuit had a lot of ringing of the VLED voltage which was probably caused by the inductance of a 3 inch cable between the dimming FET and the LED. I used a snubber circuit as suggested in TI's AN-1937 to reduce the ringing, and this led to better performance of the DIMO/DIMR pins. I was able to get the minimum on-time to 250 nsec in the lab, though I never got a spec from TI for what the minimum on-time should be.

    www.ti.com/.../snva386d.pdf