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Analyzing an LED driver waveform

Other Parts Discussed in Thread: LM3409

I recently put together an LM3409 based LED driver for driving 3 white LEDs in series. I would like to analyze the output to the LEDs to check ripple, frequency, etc to ensure it's working as designed and how various parameters change with respect to each other. However, I'm having a hard time seeing any kind of recognizable output waveform with my scope. The scope is a Rigol DS1054Z 4Ch 50MHz. At nominal voltage, my calculated frequency for the driver is 230kHz.

Is there a guide, or some tips for accurately measuring the output from my driver? I was expecting something like what is shown in the datasheet, such as: http://i.imgur.com/QLGxGF9.jpg

Can anyone provide some guidance with this? Proper methodology, recommended settings, expectations, etc. Thanks :) It's definitely a learning process.

  • The main things of concern generally for an LED driver is just the switch node (junction of Q, L, and D) voltage and the LED current/current ripple. A standard 10x voltage probe can be used on the switch node to make sure it is switching properly (solid square wave), to measure the frequency, and to measure the duty cycle. Use a current probe on a loop of wire in series with the LEDs to measure the LED current and current ripple. You can monitor any other pin (EN, IADJ, COFF, etc...) if you like (such as triggering for PWM dimming on UVLO or EN) with a standard 10x voltage probe.
  • Thanks Clinton! I did just that - and was able to see a beautiful square wave on the FET gate. It was nice to see that the square wave frequency is within 2% of the design frequency, and how input voltage affects this. Also, that the driver goes into what appears to be linear mode once input voltage drops below LED Vf.

    Do you have any recommendations or best practices for measuring current ripple without having a current probe?

  • A current probe will be the most accurate way. But if you don't have one available you can stick some resistance in series with the LEDs (maybe 100milliohm or so) and measure the voltage across it differentially with two probes. Then you can infer your current ripple from the voltage ripple on the resistor. Or if you don't need to be so accurate (and you are not using an output cap) then the LED current ripple will equal the inductor current ripple and you can use v=Ldi/dt and solve for the di since you know the voltage across it, the inductor value, and you can measure the dt with the scope.
  • Alright, so I took your suggestions and did some experiments. Here is what I'm seeing with my scope at my nominal operating Vin (14.5V). I am a total beginner when it comes to using the scope so please bear with me. Any comments or criticisms are very welcome.

    1. Here is what I see at the FET gate using AC coupling and the ground lead attached to DC ground. http://i.imgur.com/bG3uTLJ.png The frequency is within reasonable spec and it behaves as I expected with changing Vin. The duty cycle and frequency change to maintain current as measured by my multimeter. I'm curious why there is a "ghosting on the 2 outer waves in view. I believe this causes my frequency measurement to jump around between ~230kHz and the MHz range. This is the same setup with DC coupling just to show the action relative to ground. http://i.imgur.com/dKpWrAR.png
    2. If I remove the ground lead on the same setup, this is what I see. I am guessing this is incorrect and not what is actually happening. http://i.imgur.com/jZOinOF.png
    3. So then I tried to measure ripple current using two 1X probes across a 0.05R shunt, with the ground leads disconnected. After playing with the triggers I saw this: http://i.imgur.com/Uw5J3xL.png I assume this is the ripple voltage. I put an A-B differential on the screen however the number doesn't really add up to me. 100mV/0.05R = 2A? Maybe I'm just seeing noise here, or I should get each pk-pk voltage separately rather than using the math trace. What was odd to me was that it was hard to trigger this signal because it seemed to be riding on a much larger 60Hz wave, as shown: http://i.imgur.com/RJ7urTg.png Is that AC line noise?

    So, I learned some things and also asked more questions. I also made some observations. During this time, the circuit board became rather hot. Too hot to the touch, particularly the 47uH inductor. It is rated for 3.8A rms and 3.1A sat and the circuit is operating at ~2.8A. Is that something to be concerned about?


    Lastly... I had two general questions that I can't understand from reading the data sheet. Maybe you can put it into simpler terms. The undervoltage lockout - what is this used for? I have the EN pin connected to Vin, and the circuit never shuts off at the UV threshold of 10V. So, how and what is this used for? Second, what determines the best controlled off time for a given configuration? I understand that a lower frequency is more efficient due to less energy lost charging the FET gate, so how does that help you determine the best Roff and Coff? Is it simply that lower frequency = more efficiency and larger more costly components, and vice versa, or is there more to it?

    Phew. I hope that's not too much to tackle.

    Thank you

  • Alright, so I took your suggestions and did some experiments. Here is what I'm seeing with my scope at my nominal operating Vin (14.5V). I am a total beginner when it comes to using the scope so please bear with me. Any comments or criticisms are very welcome.

       1. Here is what I see at the FET gate using AC coupling and the ground lead attached to DC ground. http://i.imgur.com/bG3uTLJ.png The frequency is within reasonable spec and it behaves as I expected with changing Vin. The duty cycle and frequency change to maintain current as measured by my multimeter. I'm curious why there is a "ghosting on the 2 outer waves in view. I believe this causes my frequency measurement to jump around between ~230kHz and the MHz range. This is the same setup with DC coupling just to show the action relative to ground. http://i.imgur.com/dKpWrAR.png

       2. If I remove the ground lead on the same setup, this is what I see. I am guessing this is incorrect and not what is actually happening. http://i.imgur.com/jZOinOF.png

       3. So then I tried to measure ripple current using two 1X probes across a 0.05R shunt, with the ground leads disconnected. After playing with the triggers I saw this: http://i.imgur.com/Uw5J3xL.png I assume this is the ripple voltage. I put an A-B differential on the screen however the number doesn't really add up to me. 100mV/0.05R = 2A? Maybe I'm just seeing noise here, or I should get each pk-pk voltage separately rather than using the math trace. What was odd to me was that it was hard to trigger this signal because it seemed to be riding on a much larger 60Hz wave, as shown: http://i.imgur.com/RJ7urTg.png Is that AC line noise?

    So, I learned some things and also asked more questions. I also made some observations. During this time, the circuit board became rather hot. Too hot to the touch, particularly the 47uH inductor. It is rated for 3.8A rms and 3.1A sat and the circuit is operating at ~2.8A. Is that something to be concerned about?

    Lastly... I had two general questions that I can't understand from reading the data sheet. Maybe you can put it into simpler terms. The undervoltage lockout - what is this used for? I have the EN pin connected to Vin, and the circuit never shuts off at the UV threshold of 10V. So, how and what is this used for? Second, what determines the best controlled off time for a given configuration? I understand that a lower frequency is more efficient due to less energy lost charging the FET gate, so how does that help you determine the best Roff and Coff? Is it simply that lower frequency = more efficiency and larger more costly components, and vice versa, or is there more to it?

    Phew. I hope that's not too much to tackle.

    Thank you

  • Alright, so I took your suggestions and did some experiments. Here is what I'm seeing with my scope at my nominal operating Vin (14.5V). I am a total beginner when it comes to using the scope so please bear with me. Any comments or criticisms are very welcome.


    1. Here is what I see at the FET gate using AC coupling and the ground lead attached to DC ground. http://i.imgur.com/bG3uTLJ.png The frequency is within reasonable spec and it behaves as I expected with changing Vin. The duty cycle and frequency change to maintain current as measured by my multimeter. I'm curious why there is a "ghosting on the 2 outer waves in view. I believe this causes my frequency measurement to jump around between ~230kHz and the MHz range. This is the same setup with DC coupling just to show the action relative to ground. http://i.imgur.com/dKpWrAR.png
    2. If I remove the ground lead on the same setup, this is what I see. I am guessing this is incorrect and not what is actually happening. http://i.imgur.com/jZOinOF.png
    3. So then I tried to measure ripple current using two 1X probes across a 0.05R shunt, with the ground leads disconnected. After playing with the triggers I saw this: http://i.imgur.com/Uw5J3xL.png I assume this is the ripple voltage. I put an A-B differential on the screen however the number doesn't really add up to me. 100mV/0.05R = 2A? Maybe I'm just seeing noise here, or I should get each pk-pk voltage separately rather than using the math trace. What was odd to me was that it was hard to trigger this signal because it seemed to be riding on a much larger 60Hz wave, as shown: http://i.imgur.com/RJ7urTg.png Is that AC line noise?


    So, I learned some things and also asked more questions. I also made some observations. During this time, the circuit board became rather hot. Too hot to the touch, particularly the 47uH inductor. It is rated for 3.8A rms and 3.1A sat and the circuit is operating at ~2.8A. Is that something to be concerned about?


    Lastly... I had two general questions that I can't understand from reading the data sheet. Maybe you can put it into simpler terms. The undervoltage lockout - what is this used for? I have the EN pin connected to Vin, and the circuit never shuts off at the UV threshold of 10V. So, how and what is this used for? Second, what determines the best controlled off time for a given configuration? I understand that a lower frequency is more efficient due to less energy lost charging the FET gate, so how does that help you determine the best Roff and Coff? Is it simply that lower frequency = more efficiency and larger more costly components, and vice versa, or is there more to it?

    Phew. I hope that's not too much to tackle.

    Thank you
  • Hello. Some answers for you:

    1. First off don't measure the gate, there is more important information in the switch node itself as mentioned before (Q, L, D connection). Plus always DC couple. If there is odd jitter on that just like in the gate waveform (which there probably will be) it is likely due to the 60Hz you mention in item 3. The duty cycle would be constantly changing to regulate through the changing input voltage.

    2. Never disconnect the ground leads unless it's a special differential type probe. If you do anything you see is basically garbage.

    3. First you never want to use 1x probes. They will load whatever they are connected to and that could cause anything from an inaccurate reading to damage. Use 10x high impedance probes and do not disconnect the ground leads, ground them. In either case 2A of ripple current is unlikely but not completely impossible, but since I don't know the LED stack voltage I can't be sure. I also don't know your input source but if there is a 60Hz component on it that will make anything harder to trigger on.

    Regarding the inductor you will want to calculate your ripple current (equations in the datasheet) so you know your peak current. 2.8A average output plus 1/2 the ripple current is the peak and you may be cutting it very close for the saturation rating of that inductor. I'm not sure what inductor you are using, but some spec things very conservative and some are very liberal. But if it's getting that hot you may be close to saturation or even a bit into it. That will make everything hot. What's worse is that as the inductor gets hotter the inductance can drop and increase the peak current even more. You always want a decent amount of headroom for an inductor, you don't want to run it close to its limits (think about when the ambient temp is say 60C, it will really be hot then).

    The UVLO is there to prevent the part from trying to start until you get to a certain input voltage. There are multiple reasons people use it. It could be that the source they are using isn't capable of the increased current draw the LM3409 would present if it tried to start at a lower voltage. It could just be that you want to make sure the input is x number of volts above the LED stack voltage before it tries to start up. If you try to start below it the part will start in 100% duty cycle mode then you will get a brief flash when the input voltage gets high enough to start switching and regulating. There is hysteresis in it though that you can program (also in the datasheet) so depending on the resistor values it will start at one voltage but then as Vin decreases it will stop at a lower voltage.

    Yes, the general rule is the lower the frequency the higher the efficiency overall. But there is a point of diminishing returns. If you get too low the cost either gets too high due to component size or the DCR of the inductor will begin to dominate and kill the efficiency gains. That point is all application and budget dependent but generally you don't gain much by going below about 300kHz with most DC-DC converters.

  • Sorry about triple posting earlier. Anyway, this is exactly why i went with a ti part... awesome supporting staff and documents. Thank you! I'm going to revisit my calcs and try some further tests. I'm not sure how I overlooked that inductor rating - probably need to increase to the next package size.

    My LED stack voltage (combined forward voltage?) is around 9.9V from three Cree XM-L2 in series at 2.7A. My source voltage is 14.5V nominally but varies from 12.0 to 15.0 (typical automotive). My benchtop power supply is a 0-32V 0-8A linear analog unit with 0.1% ripple voltage rating. The goal ultimately (once I prove out and optimize this single circuit), is to put two identical circuits in parallel to run two strings independently. Hopefully they don't interfere with each other.

    Regarding the differential probe - I read that I could use two regular scope channels without ground leads to take a differential measurement, without having a special differential probe. Is that just plain wrong?

    Oh and for what it's worth, here is the circuit board I laid out. Tried to follow the guidelines the best I could: http://i.imgur.com/cOc4kCj.jpg I'm not sure what the "ringing" everyone refers to would look or sound like, but I don't think I'm experiencing that. Does it look reasonable to you?
  • It sounds like the supply is adequate, but why is there a 60Hz component on the input? That is odd unless you are having some ground loop issue between the scope and the supply. I have seen that happen. Make sure all equipment is plugged into the same place with the same ground. If you can (and sometimes it becomes necessary) you could run the scope of an isolation transformer.
    As far as the probes I am not sure. I always ground them, but it is possible there are way to use them like you mentioned. It would depend on the scope and the probes I guess. If the manual says it's ok then it probably is.
    You layout looks good. The main "ringing" most people talk about in this instance is the high frequency ringing at the switch node. With a good layout is generally isn't an issue. If the layout is really bad the ringing can get very large which can cause the source of the FET to ring will above the drain or well below ground. This could cause damage, but most often just results in radiated noise that can cause the rest of the circuit to misbehave.
  • Hi Clinton, so I took your advice and revisited my calcs. The inductor I chose was borderline for the minimum required ripple current for regulation, so I tried a lower inductance version with the same footprint, that also has a higher current rating. Here is what I'm seeing at various operating points. I was able to clear up the waveform 'ghost' by carefully bringing down the trigger from the top.

    Switch node at Vin 14.0V: http://i.imgur.com/PYxl8e3.png
    Switch node at Vin 15.6V: http://i.imgur.com/yeC2fET.png
    Switch node at Vin 21.2V: http://i.imgur.com/bdK4p0a.png (note vertical scale change)

    So this part makes sense. Higher input voltage increases the frequency, and reduces duty cycle. However I'm curious why the pattern is not consistent. It appears to alternate between a lower and higher pulse width.

    Here is the gate drive at 15.6V, showing the similar pattern: http://i.imgur.com/5dTMGE2.png

    The good news is that aside from a very slight overshoot, it appears stable! Thanks for the support. Starting to get the hang of it.
  • What you are seeing is normal. The LM3409 actually swaps the polarity of the error amp inputs each cycle. This with cause there to be a slight difference in the peak inductor current each cycle. This removes any errors from offsets in the error amp and gives you more accurate current regulation. There is some information on this in the datasheet if you are interested.

  • Hi Clinton,
    Thanks again for the help thus far. Been testing every part of the circuit and re-read the datasheet several times now. I blew one of them up and released the magic smoke when doing testing around 35V Vin. I can only assume there was some sort of voltage spike when the relay switched on and it briefly exceeded 42V.

    One thing I'm still confused about is the Under Voltage Lockout. I am using a typical R_uv1 of 16.5k and R_uv2 of 49.9k, which should create a turn-on voltage of 10V. However, my 3S white LEDs will glow as low as 5 or 6V, and the circuit ultimately goes into regulation at 11.5V, when the stack voltage is 9.8V. It seems to me that due to the dropout voltage (~1.5V?), the UVLO is basically negated since it's below the dropout voltage anyway.

    - If I don't plan to use the UVLO feature, can it be left open, or should I still connect the pin to something?
    - When you say that below the UVLO threshold, as the input voltage increases it will be in 100% duty cycle mode. Is that the same as direct drive? So, theoretically if I have an LED stack voltage of 10V at the operating point, and a UVLO set to 15V, as I increase the input voltage, it will overcurrent between 10-15V until 15V, at which point it would dim back into regulation. Am I understanding this correctly?

    and a side question...
    - It appears that the dropout voltage (minimum Vin overhead over Vout) is related to the ripple current. Is it possible to calculate the minimum overhead needed for a given config?
  • Actually those resistor values will give you a turn on voltage of just over 5V. That is why you are seeing the LEDs glow early. The part is starting up in 100% duty cycle mode so the FET is just turned full on until you reach 11.5V where it starts switching. Basically it acts as a linear regulator in dropout until the input voltage is high enough that the LED current is at the peak inductor current level during normal switching. At that point it acts as a linear regulator in regulation as you increase the input so the LED current will not increase further. Then when the input voltage is high enough to regulate while switching it begins switching and regulates to the set current value. So it is operating correctly. If for some reason you do not want to use UVLO it can be tied to VIN.

    There is no real good way to calculate the minimum overhead given that it is determined by the LED stack voltage (which varies some) and the Rds(on) of the FET used (which varies some). But if you test it out on the bench it will always be pretty close to the voltage you measure.

  • Hi again Clinton,


    Just checking in again with a couple questions. I built a single PCB using two parallel LM3409 regulators to drive two banks of high power LEDs at 2.7A each. I did this to prevent both banks from burning out should a single LED burn out, to distribute the heat load, and to stay below the recommended 5A rating for a single regulator. In the future I might try running higher currents and using a parallel LED array. Assuming I pick parts with the correct ratings, can the LM3409 drive something like 6, 9, or 12 Amps? What would you say is the limiting factor, assuming sufficient heat sinking? The PFET I am currently using is rated to 14A with a 110mOhm RdsOn and 17nC gate charge. www.digikey.com/.../3983752

    My main question is regarding the parallel circuit mentioned above (picture here: i.imgur.com/sLVnPzz.jpg) (schematic here, sans relays: http://s27.postimg.org/ksk7fsrpf/Schematic.jpg)- the only thing each regulator shares is a common source voltage (+15V and Ground). You can see that one is a duplicate of the other, just rotated 180 degrees. The issues is I am seeing a change in behavior when running each regulator individually versus together. For example - one regulator delivers 2740mA when the other regulator is disconnected, but when I connect the other regulator it drops about ~70mA and appears unstable. The source voltage is constant and the change happens instantaneously, not a function of temperature. Also, when looking at the switch node waveform with my scope, with one regulator running I get a perfect square wave that is very clean with no ringing whatsoever; however when I connect the second LED string, there is a significant amount of "jitter" and instability in the switch node. At some voltages, I noticed a flicker. It looks like the regulators are creating some kind of feedback and affecting each other. Is there a way to isolate them to avoid this interference? Is my circuit an acceptable application of the LM3409?

    It is worth noting that if I do this same experiment with two separate boards in parallel connected with ~6" wires, I don't see this issue. It leads me to believe it's a board layout issue.

    Any recommendations would be helpful.


    Thank you :)


    EDIT: Here are some scope shots to explain it better. Let me know if any more info would help.

    Gate with one driver on: http://s22.postimg.org/5eydfa3xd/DS1_Z_Quick_Print12.png

    Gate with both drivers on: http://s22.postimg.org/4ujcclaox/DS1_Z_Quick_Print16.png

    Switch node one driver: http://s22.postimg.org/gskwqheg1/DS1_Z_Quick_Print14.png

    Switch node both drivers: http://s22.postimg.org/pxt9kchup/DS1_Z_Quick_Print15.png

    Input voltage one driver: http://s22.postimg.org/92e4lcc4h/DS1_Z_Quick_Print17.png

    Input voltage both drivers: http://s22.postimg.org/qeeh6s5lt/DS1_Z_Quick_Print18.png

    LED Output one driver: http://s22.postimg.org/6nm90wvvl/DS1_Z_Quick_Print19.png

    LED output both driver:  http://s22.postimg.org/47kfn2dsx/DS1_Z_Quick_Print20.png

  • After looking at your pictures, particularly the board, I'm pretty certain layout is the issue. There are some layout guidelines in the datasheet and I don't have your full layout (inner layers if any, bottom layer) but there are still some glaring issues:

    1. Grounding is key, especially when running multiple regulators. I'm not sure if you have a ground plane either internally or on the back side, but you should. Even if you do the critical grounding points are not tied to it with vias. The switch and diode currents are discontinuous switching currents so they generate a lot of noise. The return path for these will try to follow the path of least impedance (since it is high frequency) so it will want to minimize the loop/inductance and follow the forward current paths as closely as possible. So to minimize the loops you need to have the grounds for the input caps, switching diode, and LED string as close together as possible and tied to the ground plane with multiple vias. The DAP of the IC should also be tied to the ground plane with vias. As it is now the diode ground for one regulator is closer to the input cap ground of the other so it's current return path is looping widely somewhere through the board and generating a large amount of noise.

    2. I'm not sure how the input voltage is run, but it looks like it has a lot of vias. If they are tied to a power plane it should be ok. If they are run through a trace first one then the other then it would likely still be ok if you have proper grounding. In some tough cases with multiple regulators you need to add an inductor or ferrite bead between the input of one and the other.

    3. Of lesser concern but a good practice is to analyze the current loops created on the board both when the switch is on and when the diode is conducting. The first will be through the input caps, through the switch, through the inductor, then through the LEDs. The second will be through the diode, through the inductor, and through the LEDs. If possible make sure these loops curl the same direction for each cycle. This will eliminate a field reversal and lower overall noise.

  • I forgot to answer your first question. If the FET chosen is good enough you could get up to 12A. The limiting factor is the VCC current limit, the FET gate charge, and the switching frequency. The VCC current must stay below the current limit and Ivcc = Qg*Fsw. Of course the FET thermals need to be considered depending on what the Rds(on) is.
  • Hi Clinton,

    Thanks for providing input so quickly - it's really helpful. It would have helped to post the actual layout. Any further thoughts based on this? Here is the top layer: http://s10.postimg.org/6i5b4f2vd/Top_Layer.png and here is the bottom layer: http://s10.postimg.org/ivi5bbsjt/Bottom_Layer.png

    1. I see what you're saying about my layout, it could really use some work. I have a ground "pour" on the top and bottom layer, but it is segmented by various traces. I will need to fix this, as well as the other things you pointed out. It is difficult to fit both my size limitations and optimize the layout!

    2. The input voltage is run via a huge trace on the bottom layer with a lot of vias. Another thing you might notice I did was on the IN+ pad, I stitched the top and bottom traces with vias. The idea with these was to minimize the resistance, but as I'm learning, via location and density play a bigger role on these types of circuits.

    A couple more questions came up while researching my issue.

    - Would you recommend a combination of input capacitors, such as a .1uF and 10uF, to provide better filtering for stability, or is this unnecessary? Right now I'm using two 10uF to achieve 20uF each, a number I calculated from the datasheet selecting a 6% input ripple.

    - Can you explain the purpose of the Bypass capacitor? In the datasheet and every example, a 1uF is used, but there is little explanation of its function.

    - I found some recommendations to stitch the top and bottom layer ground planes around the perimeter of the board with vias spaced ~1/4" apart. Thoughts on this as a general practice?

    - Lastly, is my PFET gate trace acceptable? It was recommended by another person that I move the components in order to shorten it, but that's not explicitly stated in any of the guidelines.

    I already started working on a new layout, placing the relays in the middle in order to shorten traces as much as possible, and separate the two regulators by a greater distance. I will post it up here before I have more boards made. Thank you again.

  • The way the ground plane is divided by the input will be an issue, even if you did have vias at the power components because you will force the return currents around that trace. So I think your idea of putting the relays and input in the middle is a good one. To answer your questions:

    1. It's always good to put a 0.1uF capacitor as close to the VIN pin as possible. After that it really just is the more the merrier, especially with multiple converters and especially with buck converters. What you have will likely be sufficient if the layout is good, but more will only help matters.

    2. It is the output of the VCC regulator. The VCC regulator powers everything in the chip, including the gate driver, so it needs a capacitor. 1uF is sufficient for any application the LM3409 can do.

    3. That is a good practice, but not absolutely necessary if you place other vias properly.

    4. Those traces should be fine.

    One last thing: Make sure and always connect the GND pin of the IC directly to the DAP beneath the IC.

  • Hi Clinton,

    Thank you for the continued support. I *think* this version is a lot better. My component selection is the same, except I added a 0.1uF input cap. Would you mind giving me some feedback on the new layout? Suggestions are very welcome. Layout: http://s7.postimg.org/6ymjv0euj/Version_2.jpg

    I also have two more questions.

    -Should the LED string (-) pad be closer to the LED (+) or to the diode ground, as I have it?

    - The datasheet suggests placing the optional output cap at the LED string if it is located far away. In my case, it is about 2 feet away through a cable. Will placing a 4.7uF output cap on the board as I have it cause issues, or is it just not ideal?

    Thanks again! I couldn't do this without your guidance.

  • That layout looks pretty good. My only suggestions:

    1. I would place the 0.1uF cap directly next to the IC VIN pin and I would give it its own via to the ground plane.

    2. Maybe it is a requirement for the particular inductor you are using, but if not I would not have holes beneath the inductors on the top layer. I have never found them to help and sometimes they can even make things worse. I would fill with continuous ground plane.

    3. I would recommend more vias. You have ground return on the top layer so maybe it's not critical, but the ground plane on the bottom will provide a more ideal path. I always recommend at least one via per 1A. So personally I would use at least 12 vias by the input cap and diode. I would add more at COUT as well and it could only help. Besides, if it's a high current design vias can only help with heat dissipation.

    Speaking of high current that board looks pretty small. Will the inductor have a high enough current rating? Will a DPak FET be able to dissipate the heat? You also may need a lot more copper such as inner ground planes with a lot of vias and/or using thicker copper such as 2oz or 4oz. I'm not sure in the end, you might be potting the board for heat dissipation. I'm just mentioning that you need to be aware of the power dissipation in each component and make sure you can get the heat out.

    As for your questions LED- is fine where it is. The capacitor is also fine on the board. But if you are PWM dimming you may need an RC snubber across COUT to stop current over/undershoots on the LED at the rising and falling edges. 2 feet of cable will give you significant parasitic inductance. If you are not PWM dimming it is just fine.

  • 1. Right on, I will certainly do that. Why do you suggest moving only the 0.1uF? Is that to damp the high frequency noise as close as possible to the IC?

    2. I removed the top layer ground pour beneath the inductor due to a recommendation I read, that the ground plane can lower the inductance. However, the specific inductor I am using is shielded and does not specifically recommend it.

    3. Okay great to know. How did you arrive at 12 vias? Each regulator is set at 2.7A average, and I have 4 vias at COUT and 4 at the diode. Just clarifying so I'm not missing something. However I did just notice that my power input ground doesn't have any nearby vias to the ground plane!

    The board is quite small, pretty much as small as I could make it. The inductor is rated for 9A IRMS and 12A ISAT, so it's well above the limit there. If you look at my earlier post showing the board that didn't function very well, I had created a small pad beneath the switch node (FET heatsink) with vias to provide a direct thermal path for that component to a heatsink. However, after testing with no heatsink or airflow for an hour, that area never exceeded 70C. The PCB I am using is a 1oz copper 2-layer FR4. The board is ultimately going into an aluminum enclosure, and I will provide a heatsink pad under each regulator.

    I am using analog dimming from the IADJ pin, so hopefully that's not an issue.

    -I was considering a placing a dozen or so more vias throughout the board to connect the top ground pour to the ground plane, just to ensure there aren't any unwanted current paths or antennas being formed. Any harm in doing this?

    Thank you
  • 1. Yes, that is exactly why you want it there.

    2. In some instances perhaps it can help depending on inductor type and what is beneath it. But usually not, especially with a shielded inductor. You will get much more benefit filling that area in with ground.

    3. I must have just read the 12A somewhere and assumed. If you are running 2.7A I think the vias are sufficient. Extra would never hurt though in the critical spots we have discussed. You can also add vias to tie the planes together anywhere you like provided you have vias in the critical high current path spots first. If you added them randomly without proper tie together at those spots you could have issues.

  • Hi Clinton,
    I received my boards and did some quick preliminary testing. Here's a picture: <s10.postimg.org/.../IMG_6858.jpg>. The good news is I no longer see the big interference that I saw before. However, I now have a different issue. The circuit is designed to deliver 2700mA, but I am seeing 2500mA on each LED string. With the previous layouts, I saw very close to 2700mA as I expected. Aside from the layout, my only component changes are: added 0.1uF input capacitor, removed RUV1 and RUV2 and connected UVLO to VIN, added 4.7uF output capacitor.

    My component selections for each bank are as follows - I obtained these by following the equations and guidelines in the datasheet:
    Coff = 470pF
    Roff = 15.4k
    L1 = 22uH
    RSns = 0.082
    Cin = 2x 10uF + 0.1uF
    Cout = 4.7uF

    Any suggestions what to check to explain this discrepancy? I appreciate it. Hopefully I'm getting closer to finishing this project. Thank you

    EDIT: I probed the switch node and noticed something I haven't seen before. http://s30.postimg.org/tl5o0njch/DS1_Z_Quick_Print27.png
    The gate is also behaving oddly. http://s23.postimg.org/vnozh5rpn/Gate2.jpg

  • It would be nice to see the inductor current waveform to be sure, but it looks like you are running at a pretty low switching frequency. 22uH is a pretty low value for that switching frequency and you may be in discontinuous conduction mode. Have you tried increasing the switching frequency?
  • I will give that a shot. Unfortunately I don't have a current probe and struggled a bit when trying to use a shunt resistor to measure current that way.


    For determining the correct inductor value, I calculated the maximum value (~35uH) so that there is sufficient ripple. I will run through the calcs again. Thanks for the tip.

  • I tried a few things. This is what I started with: http://s15.postimg.org/9bqjnqz97/standard_BOM.png

    I changed Roff to 11.7k which brought the frequency up, but still exhibited this behavior.

    Then, I changed the inductor to a 47uH I had, and this happened: http://s28.postimg.org/z6on8u00t/47u_F_and_standard_BOM.jpg

    So then I thought... what did I change since the last circuit that worked pretty well. I removed the 0.1uF input cap at the Vin pin and it went back to normal (switch node): http://s15.postimg.org/ohwleopa3/11_7k_Roff.png

    So... any idea why that 0.1uF input cap was throwing it off?

  • This can happen if there is some ground loop error at the point where the 0.1uF is located. But if it works fine without it then there is no reason not to omit it. It is uncommon for this to happen, but all it takes is some ground return path to run through that ground point and you can inject noise and cause strange behavior.
  • Interesting. This isn't an easy task at all. I'm not sure what could be causing this ground loop as I tried to make my ground plane as solid as possible. But it could be the distance between the input capacitors? I have two 10uF's near the diode, and then the 0.1uF near the Vin pin.

    I have run through the calculations many times and I'm pretty confident that I've chosen the correct values. So that just leaves layout intricacies to deal with.

    Thank you

    edit: Quick question - regarding inductor selection and ripple current. Does a greater ripple current help with more stable regulation? The reason I bring this up is because the LM3409 demo board uses a 44% ripple current (444mA), which amounts to almost 4X the minimum required for that circuit, which is 120mA. Also, the examples in the datasheet use 50% ripple current. In my circuit, I selected my inductor to minimize ripple, and stay just above the minimum requirement. Could I possibly achieve better results by using higher ripple and an output cap to stay below the peak LED current rating?

    On that note - if an LED is rated for 3A, is it a problem if the average is below 3A, but the ripple goes to say, 3.5A? Do you have any experience with how this affects an LED?

    Here is a link to my worksheet: https://dl.dropboxusercontent.com/u/28231781/LM3409%20Calculated%20v2.2.xlsx

    Maybe you can take a quick look as a sanity check?

  • Hi Clinton,

    I've had my circuit working pretty well now with a consistent looking wave form. Just one quick follow-up question. I find that once the circuit goes into regulation, the LED current is not and precisely controlled as I expected. It goes into regulation around 12V. As I vary the input voltage from 14V to 22V, the LED current will vary from 2800mA (14V) to 2700mA (16V) to 2600mA (18V), then back up to 2700mA (20V). It happens instantly as I adjust my power supply, so temperature drift isn't a factor.

    Do you have any insight as to whether or not this is normal or what could cause it? I recall on my first circuit iteration, I saw less than 20mA variance all the way from 14V to 24V. Extremely accurate regulation. I am currently using a 20uF Cin, 9.53k Roff, 10uH L, and no Cout; operating around 400kHz at nominal 14V voltage.

    As it stands this will still work for me, but it would be ideal to have better more accurate regulation since I'm on the edge of the LED ratings and cooling is limited. Thank you! Your support since the beginning of this project has been great.

    edit: After doing some research, someone here suggested a 470pF 'C0G' type capacitor for C_off. I am using all X7R in my circuit. Maybe this could help?

  • Can you use an oscilloscope to probe the switch node (CSN pin)? If it isn't a full square wave but has some ringing after the falling edge it means it is running in discontinuous mode and you may need to increase the inductor value for tighter regulation. The only reason it would vary that much is either noise due to layout or that you are running in discontinuous conduction mode which would alter the average current. Have you tried increasing the inductor value back to 22uH or even 33uH to see if that helps?
  • First to clarify, is the switch node the junction between the Q, L, and D components, or is it the CSN pin (junction of Q and Rsns)? I get different looking waveforms at these two points. (See below)

    Keeping all parameters the same, I swapped out L from 10uH to 22uH to 47uH. Here are the CSN, Switch Node, and Gate for those 3 cases at 15Vin.
    http://i.imgur.com/KVpQIvQ.jpg

    *Interesting to note that when using the 47uH inductor, I have a little better current regulation (also a higher current in the 2900mA range), but also less stability when enabling the adjacent parallel circuit. As if it's more sensitive to noise in the system. The switch node square wave will have intermittent narrow pulses that don't match a normal pattern, and the average current fluctuates on its own. My best guess is this is due to a borderline too low current ripple, and the LM3409 needs a minimum current ripple in order to maintain regulation.

    Thoughts? Thank you again.
  • Sorry for the slow response, I've been without internet for over a week. You are correct about the switch node, I misspoke about where to probe. But it looks like what you are seeing could be normal. The switching frequency and therefore the inductor current ripple will vary with the input voltage and since this is a peak current comparator the average current will shift a bit with the input voltage. This is why the average current goes up with a higher inductor value as well and also why the average changes less with lower ripple as the input voltage varies. The switching waveform also changes with higher inductor values since the different offsets in the chopping comparator become a more significant percentage of the overall current sense voltage ripple, so the waveforms you are seeing are normal. For the best line regulation you will want to use the highest inductor value you can without going below the minimum current sense voltage ripple stated in the datasheet. You will also want to use an inductor that does not lose significant inductance at the current you are running as some types can.

  • Hey Clinton, me again.

    I finalized the circuit and got it working really well on the bench. Very nice looking switch node and stable current. However when I put it in an automotive environment, weird things happen. With the engine off, at a steady 13V, I measure between 2700 and 2800mA very consistently. However, as soon as I start the engine and the average voltage increases to 14.4V, my LED current actually drops by 500mA. It's very significant. My input voltage has a +/- 0.2V ripple @ 100Hz on it. Any idea why the current would actually drop in my regulator circuit?

    As soon as the engine turns off, it increases back to where it was before.

    I checked the switch node, and while slightly more noisy than usual, it didn't look bad and I still had a decent square wave. I would really appreciate any guidance! Thank you.
  • Does it work fine with a bench supply at 14.4V input? If so the only thing I can think of is it's noise related, likely noise from the alternator. Are you using an input filter for EMI purposes? If not have you tried an input filter to cut down on alternator noise?
  • Yes it does, very stable with no issues. I think you're right that it must be due to the noise. I was hoping that connecting directly to the large battery with 3 feet of power cable would buffer that mostly out, but I guess not.

    I have not used an input filter, just the input capacitance on the circuit. Do you think an LC filter would be enough? Maybe a 100uh on the power line and 100uF to ground at the input would help? I'm not quite sure the best way to select these values. Thank you.
  • That would be a place to start. With an input filter it's pretty much trial and error until you find something that works. I would form a CLC Pi filter at the input and that should help.
  • Great, should I leave my existing input capacitance for my circuit alone and this filter would be in addition to it, or incorporate it? For example my input capacitance could become the second C of the CLC.

    What do you know - I found a nice ti document on this very subject: www.ti.com/.../snva538.pdf

    "The design of a switching power supply has always been considered a kind of magic and art, for all the engineers that design one for the first time. " Yep, that's me!! I will report back my results. It's kinda tough to experiment with this since I can't do it on the bench. Hmmphh. Thanks Clinton
  • You can use the caps you already have as the second C. I believe there are also other app notes on ti.com regarding input filters.
  • Thanks Clinton. I'm going to run some tests this weekend, starting with larger input caps and then adding a CLC filter. Unfortunately after running a frequency check the peak frequency is rather low (90-130Hz depending on engine speed) so the CLC components would need to be rather large. I think I might be better off protecting the circuit locally and preventing the noise from disrupting the IC.

    Here's the power source I'm dealing with. This is on top of ~14VDC. http://imgur.com/bxwu763

    On another note - I've had a hell of a time soldering these HVSSOP packages for prototype boards. I noticed the LM3409 also comes in a 14-PDIP. Are there any downsides to this package other than size? What about upsides, other than ease of assembly? The smaller package uses a heatsink underneath, does that mean the PDIP would need thermal considerations? I might have room on the next PCB to use that one.
  • It's probably more likely high frequency noise that is bothering things, the LM3409 should have plenty of PSRR at that low of a frequency. These parts are in many automotive designs so it should work great if filtered correctly. You should also be fine with a PDIP if you prefer. It is not as good thermally but usually that is only an issue at high input voltages and high switching frequencies since the 09 is a controller.
  • Great news Clinton - it works beautifully. I learned a valuable lesson over the weekend: the final installation makes a big difference. I installed the circuit board in its final resting place in an aluminum housing, attached to the full 6 foot length of cable, and the issue is no more. With the engine off - 2702mA. With the engine on - 2704mA. With the engine revving - 2704mA. It's almost surreal just how stable it is. The switch node has a perfect square wave with high stability even as it warms up. I did notice a periodic drop in the current - every 5-10 seconds the current would drop by ~50mA then bounce back up, but adding a 100uF electrolytic input cap eliminated this.

    My only idea as to why it works now is the aluminum housing and the length of wire. Apparently enough wire (in this case, about 12 feet 18AWG round trip) can provide parasitic inductance, which in this case adds stability.... maybe.

    I think that will be all for now - until the next hurdle comes along! I want to thank you for your continued support over the past year, I really couldn't have done it without this support forum. I have a few things I would like to add on the next iteration (many months away), such as a temperature-related dimming scheme. Maybe a simple thermistor added to the I_Adj pin is all it would take? The struggle is how to mount it remotely (ie. in a separate light housing).

    Anyway thank you so much!!