TPS61181 design consideration

Hi TT_Jefer,

I'm familiar with using the TLC59116 and the TLS5925 to accomplish this. Overall, the method to chose mainly depends on how many strings you want to control, the voltage you have available to power the LEDs, and the power dissipated based off the current and voltage at the device.

If you want to control more strings, you will use a lower amount of LEDs in series.

Lowering the number of LEDs in series also means you're able to drive the LEDs with a lower voltage. Having 8 or 10 LEDs in series means you need to have at least 29.6V or 37V above the minimum output voltage in order to drive the LEDs.

Finally, having a higher voltage at the outputs mean that more power is being dissipated by the device. You will need to watch the power dissipation or else the device will hit thermal shutdown (if available) or the device will be damaged.

I would look into the TLC59116 so that you can lower the voltage needed to power the LEDs, and have more control of the LED strings.

Let me know if you have any other questions.

Hi Harry,

Okay,thanks for your suggestion.

By the way, do you know who is in charge of TPS61181 of TI engineer on E2E forum?

I would like to discuss TPS61181 with him.

Thank you!

Hello Jefer,

Using more LEDs in series will increase the boost output voltage on TPS61181. That will increase the conversion ratio of the boost converter and reduce efficiency. Although the LED driver headroom losses are smaller relatively with higher output voltage, the boost converter efficiency is the dominating factor. This all depend of course on the input voltage and chosen external components, but as a general guideline you will get better efficiency with 5 x 8 configuration.

10 LEDs with max Vf yields 37V Vf and then you have to take the current sink headroom voltage into account, so you would get quite close to the 38V op max specified output voltage for TPS61181. In that sense the 8 LEDs in series would be safer option.

Hope this helps.

Thanks.

Best Regards,

Tomi Koskela

Hi Tomi,

Thanks for your comment.

By the way, attachment are our schematic and layout files.

could you please help us to review it and provide your comment if needed?

Thanks!

JeferTPS61181_review_1119.zip

Hi Jefer,

I reviewed the schematic and layout. I could not figure out all the layers etc. on the layout, but anyway here's some comments:

- Diode(s) seems to be little over specified (10A). Peak repetitive current should be >1.5A

- Inductor current rating is also quite high (5.5A). Max current rating should be >1.5A. You could also consider 10µH inductor for better efficiency.

- I could not see the boost input capacitor in the layout. Power rail goes to another layer and could not follow it. Anyway the loop area for when boost SW is conducting / not conducting should be minimized. That means SW node should be as short as possible and input/output capacitors as close to the SW node as possible. Also the PGND pin and input/output capacitor GND should be as close as possible. So if you could use smalled diodes, you could get the inductor closer to the SW pin and the SW route smaller. You can also consider moving the EN / Fault resistor etc. further away, so you can get the inductor closer to the SW pin.

- Separate PGND and SGND planes/areas is recommended. PGND for boost high power switching return current (PGND pin, and boost input/output capacitor grounding) and SGND for more sensitive signals (SGND pin, VBAT capacitor grounding). I could not follow the layout gnd planes, maybe it is already done this way, but anyway worth checking.

- Last - I had to flip the design to get the pinout to match. Please check that the chip top view pinout matches the datasheet. Again, it might be ok and I'm just looking at the wrong side of the board, but worth checking.

 

Thanks.

Best Regards,

Tomi Koskela

Hi Tomi,
Okay, Thanks for your support!

Sincerely,
Jefer