LM3429 Driver performance anomalies after test burn-in

I tried to recreate the conditions I saw before, and what I noticed was after a while of being on the output began to flash brightly, not the same as it does with a high voltage input. It would go on for a moment at full brightness and the go off again, slowly strobing like this. Could this be an issue caused by heat?

I was thinking more about the V in affecting the output of U2. It could potentially be a noise on the serial lines that is prohibiting the digital potentiometer from receiving the SPI commands? I noticed at lower voltage input levels the noise I see on the scope is significantly larger. It seems actually that at one point in the range it just steps up and the noise suddenly doubles. I've still to look into this further, and I may try adding some noise suppression to the CLK and MOSI lines.

I'm wondering if upping the layout to a 4 layer PCB might help this or if it's even something that is resolvable when trying to design a driver with such a huge in/out voltage difference and high current requirement.

It sounds like it could be noise related, and that is usually due to layout. The peak switching currents are much higher at lower input voltages so there will be more noise. That is the case with any boost or buck-boost converter. If you could provide the layout that matches the schematic I would be happy to look it over for issues. If you do go to a 4 layer board that makes layout even easier if the layout is indeed the problem.

That would be very much appreciated. 

Here's the layout, top and bottom. 

EDIT: better resolution...

I would post the full schematic too, but it's a little sensitive to publicly make available. To fill in some blanks though: U1 is another buck converter that provides 3.3V to U2, the microcontroller.

Ok, here are my observations. Any single one, or a combo, could cause some issues. Some are more major than the others. In any case I'm not sure if any of this is the issue, but it's quite possible.

1. I noticed the HSP sense trace runs directly next to the switch node. You have the filter there so this is probably not an issue, but it could be depending on other noise generators. Either way it is always best to route current sensing nodes away from high dv/dt and di/dt spots if possible.

2. Grounding. This is why I say a ground plane is so useful. You would like to have the PGND of the IC tied close to, and directly to the ground of R30 and close to the input cap ground if possible. As it is the grounding is very cut up, it is possible to have the IC ground at a potential different than the R30 ground which could cause misbehavior. Just as important in this case is the return current path. If you imagine the forward current path when the switch is on from Cin, through L, the FET, and then R30, there will be a ground current return path that would like to follow the path of least impedance. That means the ground return path wants to follow the forward return path as closely as possible. In this case the ground return path cannot, so it will find its way on some other path of least impedance. This will for a loop, making a nice radiator, and also possibly causing some points to not be at the same ground potential as other points. Grounding is the most common layout issue by far.

3. Thermal reliefs. I notice that you are using them in some spots. That's ok for low current stuff, but my main concern is where there are high currents. I would not use any for the high current switching path components, or make the connections more beefy. The real concern is R30. You could fuse those reliefs with that amount of current if the vias aren't sufficient or the current wants to go another way.

4. Input capacitance. The amount is fine, but it's too far away to filter effectively for the IC VIN. That is ok if you filter VIN some other way. I would recommend an 10ohm resistor from VCC to VIN and a 1uF ceramic capacitor from VIN to ground.

5. The last pertains to R30 and IS again. The other concerns I have here are the vias and where IS is connected. From the FET source you go through 3 vias, then through a relatively small back side trace, then back up through 3 vias to R30. The first potential issue is the number of vias and the back side trace. You will have pretty high peak currents, particularly at lower input voltage. I would actually be surprised if the vias, trace, or both fuse over time and become more and more resistive. That could cause big problems, especially where you are connecting the IS pin which is before that current path. If it is becoming any more resistive and you sense IS where you are it will think it should be current limiting when it shouldn't really.

Hopefully that helps. I know it can be annoying to rev a board, but switchers can be difficult to layout given the noise they generate. I would recommend a 4 layer board if you can. That makes life much easier. I would make the second layer a solid ground plane and tie all ground points to it really well with vias. You could make the 3rd layer all VCC and that would really make routing easy.

By the way, what inductor are you using. I have seen issues where when the inductor gets hot it loses inductance and could saturate. That doesn't sound like the case here, but the inductor is critical so it's good to know that it's rated properly.