Operating the TPS92512 with digitial dimming and output voltage near input voltage

Hello,

Increasing the inductance and lowering the frequency will allow Vin to be closer to Vout.  Check your design with:

If this happens only when dimming it's possible something else is happening.  Vin close to Vout causes a longer start-up delay due to the available voltage for the inductor to charge.

Thanks,

Clinton,

I have updated my post to add clarity: this is digital dimming via the PDIM pin on the TPS92512HV.  I can see that decreasing the value of the inductor helps in this regard but wonder what negative side effect such would have; the app note recommends calculating the maximum inductor value possible (min input voltage, max output voltage, ripple current set at 75mA) and then select the next size down for inductance value, but such results in a 56uH inductor, while I'm better off (at least for this situation) going smaller than the 47uH inductor I have in place (the 33uH inductor on the evaluation board performs a bit better).  I've got a few smaller inductor values I could try, not sure what other tests to run to disclose the potential negative side-effects.

Michael

Michael has run some more tests and communicated the following with me today:

- The voltage on the boot cap falls off at about 1V every 1.5mS when digital dimming is active (that is PDIM goes low and the LED current turns off to dim the LED); when "good" the boot cap voltage is right about 6V, and it becomes a problem when it gets under 2.4V

- For the 10KHz PWM I'm using on PDIM with 50% duty the off time is 50uS, so the boot cap voltage falls very little (still very close to 6V, so nowhere near the 2.4V trouble level)

- Even for a 1KHz PWM at 50% duty the off time would be 500uS, meaning the boot cap would lose about 300mV

- Both the above have instability problems (the current out to the LED string is inconsistent) at a certain input voltage, but when changing to 100% duty (no digital dimming) the problem (instability) goes away and the current to the LED string is beautifully consistent

 The above shows that this isn't a boot cap voltage depletion problem; not sure what is causing the instability with digital dimming, but this is the issue I need to improve.

Any further feedback or input is welcomed and appreciated!

This is a very hot issue for Michael.

Thanks again!

Paul

I won't be sharing any information on-line, if we were dealing directly with each other I'd be glad to, but I can tell you that the TPS92512HV eval board has the exact same problem, and my board's circuitry is very close to that, here are the difference down to the gnat's ass, where "I" refers to my design and "they" refers to the evaluation board:

1. UVLO detection: I have 200K high to 10K low so 4.76% transfer, they have 174K high to 20.5K low so 10.5% transfer (so they detect under-voltage at a lower voltage)

2. RT/CLK: I have 200K to ground, they have a 191K resistor to ground, so their switching frequency is slightly higher.

3. Inductor: I have a 47uH rated for 2.6A RMS and 2.5A saturation, they have a 33uH rated for 3.0A and 2.8A saturation.

4. Current feedback resistor: I have a 0.1ohm while they have a 0.2ohm that I changed to 0.14ohm by adding a 0.47ohm atop the 0.2ohm (I made this mod to the eval board to increase current capacity a tad)

5. I_ADJ input pin: I have a 0.1uF ceramic cap, they have 0.01uF

Understood. If need be you can send me a friend request so we can communicate privately and we can exchange e-mails directly. But in the mean time is there any way you could share some waveforms? A couple good ones would be dimming where you are having this issue with one shot being multiple cycles and one shot zoomed in to the leading edge. Of particular interest would be the PDIM, PH, and LED current waveforms together.

I can also try this in the lab sometime this week since you have told me what needs updating on the EVM, but please let me know the exact input/output voltage conditions you are using. But some things that may be worth trying:

1. Use more input capacitance. When PWM dimming the input takes a lot more stress, I generally recommend at least 10x when PWM dimming in most cases. This of course really depends on the supply you are using and the lead lengths to the board (double check your supply too to make sure it isn't borderline current limiting).

2. I am not sure exactly what you are driving PDIM with, but perhaps it is noisy or has insanely fast slew rates? To be sure it wouldn't hurt to try putting a 1k resistor in series with the PDIM pin, and maybe a small (1nF maybe?) capacitor to ground for some protection and filtering.

3. PWM dimming can stress the inductor a bit more, you will have higher peak currents during startup to try and charge the output quickly. As an experiment may try to use an inductor with a significantly higher saturation current rating just to see.

I also noticed that I forgot to answer one of your earlier questions: No, there is no problem using a lower inductor value than that calculated in the datasheet. It will only affect your maximum analog dimming range if you were using it.

Ok, I was able to reproduce the behavior on the bench. It looks like a stability issue that can occur at high frequency dimming. I spoke with the IC designer and he confirmed he suspects that as well from the behavior. The COMP cannot react fast enough to reach a steady state value each cycle. I increased the bandwidth by using a type II compensator (470pF from COMP to ground plus series 887ohm + 4.7nF from COMP to ground) and it helps just slightly at 10kHz, a little more at 1kHz. But the root cause is that when the input gets very close to the output there is not much room for duty cycle correction, or to put it another way you have very low bandwidth regardless of your compensation components. Basically you need about 6V or more of headroom to have enough bandwidth in this application to PWM dim at 10kHz. So there is a limitation on PWM frequency versus Vin/Vout headroom to maintain stability.

One other question regarding the TPS92512HV: the recommended operating condition is for a max junction temperature of 125 degC, the absolute maximum junction temperature is listed at 150 degC, and the thermal shutdown feature occurs at 165 degC typical; is this a mis-print, odd specmanship, or is this thermal protection a feature that's not intended for use?  I've been using that thermal protection feature to make a robust and darn near bullet-proof design, but if I believe the spec verbatim I should be steering clear of it... if I make absolutely sure the junction temperature is 150 degC maximum I'll end up with a design that doesn't meet my needs.  What is the point of a shut-down feature that occurs above the absolute maximum?