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WEBENCH® Tools/LM3429-Q1: Not performing as Designed in Webench. 250mA instead of required 2A.

Part Number: LM3429-Q1

Tool/software: WEBENCH® Design Tools

Hello,

I have designed a led driver for use with a Cree XHP70 LED powered by a 5 cell lithium battery, however i anticipate that i will also use this for an automotive application as well.

I have constructed the circuit and it does work however the output performance is troubling me.

The design specifications are:

Input : 11v - 22v

output: 12.6v @ 2.2A

But when i measure the voltage and current i get an output of 11.25v @ 0.25A.

I do not know how to tackle this problem as this is my first LED driver design and I cannot get a good grasp on the calculations in the data sheet.

Can someone please help me with this?

Here is the webench link to the design

also attached are the webench report, my eagle schematic file and parts list.

as this was my first attempt at surface mount parts as well I tried to keep the majority of my parts at 1206 so i could handle them and use a soldering iron if required.

37 actual build components.pdf

37 REPORT.pdf

  • Hello Roy,

    I think the webench design looks ok, but I don't see your actual schematic attached. Could you provide that? It would also be good to see a switching waveform (drain of M1) to see how it is behaving. Sometimes layout issues can cause problems and you can generally tell if you have issues by the switching node waveform.

    Thanks,

    Clint

  • Hi Clint, thank you for wanting to help.

    I can only give you a waveform from webench as I don't have the tools to capture that information from my prototype.

    I was in a hurry yesterday and missed the schematic, sorry.

    Here is it:

    37 01.sch

    37 02.brd

    37 Simulation data report.pdf

  • Hello Roy,

    Thanks. Unfortunately I don't have the right software to view those. Would it be possible to get pdfs or even just screen capture pictures? If not I can talk to some folks and see if we have any software available that can open them.

    Thanks,

    Clint

  • HI Clint,

    Here is a pdf with the eagle schematic, and the top and bottom board layout

    0284.DRIVER.pdf

  • Hello Roy,

    Where is the Riadj from the components list? I'm just curious, but it looks like your schematic is ok. I do have concerns about the pcb. Not only the layout because switchers generate a lot of noise but also whether there is enough heatsinking for 25W+. Can you get a switching node waveform on the drain of the FET? That would really tell us for sure. In either case there are for sure some layout issues. I will write up a review and list of suggestions tomorrow if that is ok. Switcher layout isn't easy for sure, but a switching waveform would easily tell us if that is the likely cause.

    Thanks,

    Clint

  • Sorry for that, i designed Radj to go between P1 and P2 for anologue dimming. however P1 and P2 are bridged at the moment.
    I have a large heat sink to use, currently the circuit gets to 35 degs in open air.
    I'm not sure if i can get a waveform for you but i'll see what i can do.
  • another thing i'd like to ask is does D1 need to be as highly rated as it is at 100V 20A, or can it be brought down to something like a 40V 5A schottky diode? I would like to reduce its footprint.
  • Hello Roy,

    To answer the diode question yes you can use a 40V schottky. The FET/diode voltages will be Vin+Vout so the FET could be a 40V FET as well under your conditions.

    On to the issue you are having, I am pretty certain it is a layout issue unfortunately. Here are the main concerns I see:

    1. Grounding. If possible it is always good to have a dedicated ground plane that all grounds are solidly tied to. But most importantly with this topology is that the ground for Rcs is tied very well to the IC grounds/DAP. In your case if you end up with a smaller diode package you may be able to extend ground around it, cut into the input plane beneath the IC and extend ground to there, and add vias to the IC DAP to tie it directly to the bottom ground plane that Rcs already ties to. As it is now I am pretty sure the grounds for those two points are quite different at these current levels (especially when you include 2 and 3 below). The part is probably falsely triggering current limit due to that.

    2. Vias. I noticed you basically have just a single via in most places. I usually use 1 via for every 250mA if I have plenty of room, but I'll go as much as an amp per via if really constrained. You will be looking at peak switching currents of nearly 3A at your minimum input voltage. Insufficient vias will also cause errors just as inadequate grounding does. I would recommend (along with vias in the IC DAP pad) that you use at least 3 vias where Rcs ties to ground. I would also use at least 3 vias where IN+ ties to the bottom IN+ plane, where the IN+ plane ties to the output capacitors, where the diode ties to the output capacitors, and where the FET ties to the diode.

    3. Trace widths. I think with extra vias most of the traces are ok. But one that does concern me is the trace from the FET to Rcs. Again, this trace will see about 3A of peak current but it is no wider than the pins of the IC package. That will for sure cause IS errors and will likely open like a fuse before long.

    I know you probably hate to hear that it's a layout issue because that means fabricating more boards. If it were easier to access the DAP, say from beneath if the IN+ plane wasn't there, you could try shoring up the grounding a bit and see if it helps at all. You could also solder solid wires through the vias to improve them. But it's hard with this layout to improve the grounding. Maybe you could solder some wire directly from the PGND pin to the Rcs resistor? In any case you probably would not get it fully working, but if the amount of output current you get goes up then you know you are on the right track.

    I hope this helps.

    Regards,

    Clint

  • Thanks for you time Clint.

    I'll try the wire between PGND and RCS. That will give me an idea.

    I am trying to line up a oscilloscope to get you a waveform of the drain on M1, it might be next week before i can get it.

    Thanks, Roy.

  • Clint, the wire between PGND and RCS improved performance from 260mA to about 900mA.

    This shows that I need to drastically improve on the pdb layout.

    Having constructed this prototype, I am redesigning the board to use 0805 sized components which will give me more options for the layout. 

    I will also take note on your other suggestions regarding the ground plane, vias and trace widths.

    I will still try to get the waveform to look at.

  • Hello Roy,

    Yeah, that is a very good indicator. If you can use more than 2 layers it makes life easier, but I understand the cost associated. Packing low current signal components in and expanding the ground plane as much as possible will help, along with my other suggestions. Switchers by nature generate noise and probably 1/3 of the issues I see are due to layout, it isn't easy. I would be happy to review your next layout before you spend money fabricating boards. Just let me know.

    Best regards,

    Clint

  • Hello Clint.

    I have had a chance to create a new design, would you mind having a look at it?

    I think I've made all the required changes.V2 no 49_9.pdf

  • V2 no 49_9 recs.pdfHello Roy,

    It looks pretty good. I like to have a little more solid grounding and ground return paths, especially at those current levels. So here is a pdf markup with my suggestions. It's not too much, just adjusting for tying the grounds together better.

    Regards,

    Clint

  • HI Clint, what do you think of this one?V2 no 49_10.pdf

  • Hello Roy,

    I think that looks good, especially with your size constraints. It always gets more difficult when you are trying to pack a lot into a small space.

    Regards,

    Clint

  • Hi Clint, I'll get a few boards made and go from there.
    Thank you again for the help, I really appreciate it.

    Roy.